Time-sharing telecommunication system with logic circuitry for classifying line-voltage changes of different duration

Claim 2

In a telecommunication system having at least one channel switchable between two significant states of energization in relatively short pulsing cycles and relatively long switching intervals, the combination therewith of a source of sampling pulses with a recurrence period substantially shorter than any of said pulsing cycles; circuit means responsive to said sampling pulses for generating either of two types of control pulses signifying the instantaneous state of energization of said channel; a network with a first group of outputs assigned to one of said states of energization and a second group of outputs assigned to the other of said states of energization of said channel, the outputs of each of said groups including a first output for a starting signal occurring upon a changeover from the other group, a second output for a transition signal and a third output for a permanence signal, at least the first and the second output of each group including each a plurality of terminals for developing a stable form of the corresponding signal on one terminal and at least one unstable form thereof on another terminal, said network having inputs connected to receive said control pulses and said test pulses and further having circuitry for translating said two types of control pulses into output signals on said first and said second group of outputs, respectively, with switchover between different outputs of the same group in response to said test signals upon perseverance of the corresponding state of energization of said channel, said circuitry responding to coincidence of either form of starting signal with a test pulse for generating a corresponding form of transition signal and to coincidence of either form of transition signal with a test pulse for generating said permanence signal, said circuitry further responding to coincidence of said stable form on a terminal of one group with a control pulse of the type signifying the opposite state of energization for generating an unstable form on a terminal of the same group and to coincidence of an unstable form on a terminal of one group with a control pulse of the last-mentioned type for generating the stable form of a corresponding pulse on an output terminal of the other group; and an evaluating circuit connected to certaiN of said outputs for generating distinctive classification signals in response to output signals thereon.

Claim 3

The combination defined in claim 1 wherein said channel is a subscriber line provided with digital selector means for generating dialing pulses following one another within a digit with a cadence corresponding to said relatively short pulsing cycles, trains of said dialing pulses being separated by interdigit pauses corresponding to said relatively long switching intervals, said line having an open-circuit state of energization assigned to said first group of outputs and a closed-circuit state of energization assigned to said second group of outputs, said evaluating circuit including first gate means for generating a line release signal in response to the permanence signal of said first group, second gate means for generating an interdigit pause signal in response to the transition signal of said second group, and third gate means for generating a dialing pulse signal in the presence of an output signal of said first group and in response to a control pulse of a type giving rise to a starting signal of said second group.

Claim 4

The combination defined in claim 1 wherein said circuitry responds to coincidence of an unstable form of said starting signal with a test pulse for generating an unstable form of said transition signal on a terminal of the same group.

Claim 5

The combination defined in claim 3 wherein said channel is a subscriber line with alternate open-circuit and closed-circuit states of energization, said first group of outputs being assigned to said open-circuit state and including as its first output three terminals for a stable form B and two unstable forms B1, B2 of the starting signal, as its second output three terminals for a stable form B'' and two unstable forms B1'', B2'' of the transition signal, and as its third output a single terminal for the permanence signal R; said second group of outputs being assigned to said closed-circuit state and including as its first output three terminals for a stable form C and two unstable forms C1, C2 of the starting signal, as its second output three terminals for a stable form C'' and two unstable forms C1'', C2'' of the transition signal, and as its third output three terminals for a stable form H and two unstable forms H1, H2 of the permanence signal; said control pulses being of a first type Q assigned to said open-circuit state and of a second type P assigned to said closed-circuit state; said circuitry responding to coincidence of a control pulse P with the stable form B, B'' for respectively generating the first unstable form B1, B1'', to coincidence of a control pulse P with the second unstable form B2, B2'' for invariably generating the stable form C, to coincidence of a control pulse Q with the second unstable form B2, B2'' for generating the first unstable form B1, B1'', and to coincidence of a control pulse Q with the first unstable form B1, B1'' for respectively generating the stable form B, B''; said circuitry further responding to coincidence of a control pulse Q with the stable form C, C'', H for respectively generating the first unstable form C1, C1'', H1 to coincidence of a control pulse Q with the first unstable form C1, C1'', H1 for respectively generating the second unstable form C2, C2'', H2, to coincidence of a control pulse Q with the second unstable form C2, C2'', H2 for invariably generating the stable form B, to coincidence of a control pulse P with the second unstable form C2, C2'', H2 for respectively generating the first unstable form C1, C1'', H1, to coincidence of a control pulse P with the first unstable form C1, C1'', H1 for respectively generating the stable form C, C'', H; said circuitry further responding to coincidence to a test pulse Z with any form of starting signal of either group to generate the corresponding form of transition signal within the group, to coincidence of a test pulse Z with any form of transition signal B'', B1'', B2'' of the first group to generate the permanence signal R thereof, and to coincidence of a test pulse Z with any form of transition signal C'', C1'', C2'' of the second group to generate the stable form H of the permanence signal H.

Claim 6

The combination defined in claim 4 wherein said network comprises a logic matrix with 16 output terminals for said output signals and coding means connected to said output terminals for translating said output signals into respective four-bit binary words, said logic matrix having eight input terminals connected to receive the original and inverted forms U1, U2, U3, U4 and U1, U2, U3, U4 of the bits of said binary words and three further input terminals connected to receive said control pulses P, Q and said test pulses Z.

Claim 7

The combination defined in claim 5 wherein said output terminals include a first terminal SO for the signal R, a second terminal S1 for the signal B'', a third terminal S2 for the signal H1, a fourth terminal S3 for the signal B1'', a fifth terminal S4 for the signal B, a sixth terminal S5 for the signal H, a seventh terminal S6 for the signal C1, an eighth terminal S7 for the signal C, a ninth terminal S8 for the signal B2, a 10 terminal S9 for the signal B2'', an 11 terminal S10 for the signal H2, a 12 terminal S11 for the signal B1, a 13 terminal S12 for the signal C'', a 14 terminal S13 for the signal C1'', a 15 terminal S14 for the signal C2 and a 16 terminal S15 for the signal C2'', said coding means converting said output signals into the binary equivalents of the subscripts of the respective terminal designations.

Claim 8

The combination defined in claim 2 wherein said subscriber line is one of a plurality of such lines connected for consecutive scanning during successive cycles of predetermined length, said sampling pulses and said test pulses each having a duration equal to a scanning cycle and being concurrently applied to all said lines.