Frame synchronizing circuit

Claim 2

A frame synchronizing circuit, comprising: signal separation means for separating an input signal, having a frame synchronizing pattern periodically inserted therein, into a predetermined number of signal trains; frame synchronizing pattern detection means for detecting modified frame synchronizing patterns in the signal trains; frame pulse output means for outputting a frame pulse with a timing corresponding to the period of the frame synchronizing pattern in the input signal; timing comparison means for producing a noncoincidence signal indicating noncoincidence of the frame pulse and each of the modified frame synchronizing patterns; synchronization guarding means for discriminating whether the frame pulse is synchronized with one of the modified frame synchronizing patterns; and timing control means for adjusting the timing of the frame pulse when said timing comparison means detects noncoincidence and said synchronization guarding circuit indicates asynchronization of all of the modified frame synchronizing patterns.

Claim 3

A frame synchronizing circuit as recited in claim 1, wherein said frame synchronizing pattern detection means detects the predetermined number of modified frame synchronizing patterns and comprises modified frame pattern detection circuits, operatively connected to said signal separation means, said frame pulse output means and said timing comparison means, each of said modified frame synchronizing pattern detection circuits detecting one of the modified frame synchronizing patterns, wherein said timing comparison means comprises timing comparison circuits, each of said timing comparison circuits operatively connected to a corresponding modified frame synchronizing pattern detection circuit, said frame pulse output means and said synchronization guarding means, for generating a noncoincidence signal indicating noncoincidence of the frame pulse with the modified frame synchronizing pattern detected by the corresponding modified frame synchronizing pattern detection circuit, and wherein said synchronization guarding means comprises synchronization guarding circuits, each of said synchronization guarding circuits operatively connected to a corresponding timing comparison circuit, said frame pulse output means and said timing control means, for producing a synchronization signal indicating synchronization of one of the modified frame synchronizing patterns with the frame pulse in dependence upon the noncoincidence signal output by the corresponding timing comparison circuit.

Claim 4

A frame synchronizing circuit as recited in claim 2, wherein said signal separation means separates the frame synchronizing pattern into partial frame synchronizing patterns in the signal trains, respectively, and wherein each of said modified frame synchronizing pattern detection circuits monitors all of the signal trains and combines all of the partial frame synchronizing patterns in detecting the modified frame synchronizing pattern corresponding thereto.

Claim 5

A frame synchronizing circuit as recited in claim 2, wherein the input signal comprises a plurality of multiplexed data channels, and wherein said frame synchronizing circuit further comprises switching means for discriminating which of the modified frame synchronizing patterns is in synchronization in dependence upon the noncoincidence and synchronization signals output by said timing comparison circuits and said synchronization guarding circuits, respectively, and for assigning the signal trains to output channels having an unvarying correspondence to the data channels.

Claim 6

A frame synchronizing circuit as recited in claim 2, further comprising clock signal generation means for generating a clock signal in phase with each of the signal trains in dependence upon the input signal, wherein said frame pulse output means comprises a counter, operatively connected to said clock signal generating means, said timing control means and said timing comparison circuits, for counting the clock signals under control of said timing control means and outputting the frame pulse every time a maximum count is reached, and wherein said timing control circuit comprises a phase lock circuit for generating a timing adjustment signal in dependence upon the noncoincidence and synchronization signals output by said timing comparison circuits and said synchronization guarding circuits, respectively, the timing adjustment signal inhibiting a single pulse of the clock signal from being applied to said counter.

Claim 7

A frame synchronizing circuit as recited in claim 2, wherein said frame synchronizing pattern detection means further comprises shift registers, each operatively connected to said signal separation means and all of said modified frame synchronizing pattern detection circuits, for shifting a corresponding one of the signal trains, and wherein each of said modified frame synchronizing pattern detection circuits comprises a gate circuit, operatively connected to selected portions of said shift registers for detecting of all bits of a corresponding one of the modified frame synchronizing patterns.

Claim 8

A frame synchronizing circuit, comprising: a series-parallel conversion circuit, operatively connected to receive a serial signal containing multiplexed channels and a frame synchronizing pattern inserted periodically therein, for separating the serial signal into a predetermined number of signal trains having bits, shift registers, operatively connected to said series-parallel conversion circuit, each of said shift registers receiving one of the signal trains; gate circuits, each of said gate circuits operatively connected to all of said shift registers, for selectively combining the bits of the signal trains stored in said shift registers to detect a corresponding one of the predetermined number of modified frame synchronizing patterns; clock signal generating means for generating a clock signal in phase with the signal trains from the serial signal; a frame pulse generating circuit for counting pulses in the clock signal and for producing a frame pulse in synchronism with the period of the frame synchronizing pattern; timing comparison circuits, each of said timing comparison circuits operatively connected to a corresponding one of said modified frame synchronizing pattern detection circuits, said clock signal generating means and said frame pulse generating circuit, for producing a noncoincidence signal indicating noncoincidence of the frame pulse and the detecting of the corresponding modified frame synchronizing pattern by the corresponding gate circuit; synchronization guarding circuits, each of said synchronization guarding circuits operatively connected to a corresponding one of said timing comparison circuits and said frame pulse generating circuit, for producing an asynchronization signal indicating asynchronization of the corresponding modified frame synchronizing pattern in dependence upon consecutive repeated output of the noncoincidence signal by the corresponding timing comparison circuit; and a phase lock operation discrimination circuit, operatively connected to said frame pulse generating circuit, said clock signal generating means and all of said timing comparison circuits and said synchronization guarding circuits, for inhibiting a single pulse of the clock signal in dependence upon the noncoincidence and asynchronization signals output by said timing comparison circuits and said synchronization guarding circuits.

Claim 9

A frame synchronizing circuit, comprising: a series-parallel conversion circuit, operatively connected to receive a serial signal containing multiplexed channels and a frame synchronizing pattern inserted periodically therein, for separating the serial signal into a predetermined number of signal trains having bits, shift registers, operatively connected to said series-parallel conversion circuit, each of said shift registers receiving one of the signal trains; gate circuits, each of said gate circuits operatively connected to all of said shift registers, for selectively combining the bits of the signal trains stored in said shift registers to detect a corresponding one of the predetermined number of modified frame synchronizing patterns; clock signal generating means for generating a clock signal in phase with the signal trains from the serial signal; a frame pulse generating circuit for counting pulses in the clock signal and for producing a frame pulse in synchronism with the period of the frame synchronizing pattern; timing comparison circuits, each of said timing comparison circuits operatively connected to a corresponding one of said modified frame synchronizing pattern detection circuits, said clock signal generating means and said frame pulse generating circuit, for producing a noncoincidence signal indicating noncoincidence of the frame pulse and the detecting of the corresponding modified frame synchronizing pattern by the corresponding gate circuit; synchronization guarding circuits, each of said synchronization guarding circuits operatively connected to a corresponding one of said timing comparison circuits and said frame pulse generating circuit, for producing an asynchronization signal indicating asynchronization of the corresponding modified frame synchronizing pattern in dependence upon consecutive repeated output of the noncoincidence signal by the corresponding timing comparison circuit; and a phase lock operation discrimination circuit, operatively connected to said frame pulse generating circuit, said clock signal generating means and all of said timing comparison circuits and said synchronization guarding circuits, for inhibiting a single pulse of the clock signal in dependence upon the noncoincidence and asynchronization signals output by said timing comparison circuits and said synchronization guarding circuits.