Cell-structured digital multiplier of semi-systolic construction

Claim 1

A cell-structured, digital multiplier of semi-systolic construction, wherein all the bits of the multiplicand are respectively AND-logic-linked to one bit of a multiplier to form a group of partial product bits, and one such group is formed for each multiplier bit, comprising a first plurality of cells arranged in a first row which generates a first group of partial product bits and said first plurality of cells receiving all of the multiplicand bits to AND-logic-link them to the lowest value multiplier bit, further plurality of cells contained in further rows following said first row and assigned to further groups of partial product bits, and the cells of each further row generate the partial product bits formed by an AND-logic-link of all the multiplicand bits to one single multiplier bit, and the value of the multiplier bit which is used increases from row to row, a first plurality of input lines to which the multiplicand bits are supplied and said first plurality of input lines connected to selected ones of said cells, a second plurality of input lines to which the multiplier bits are supplied and said second plurality of input lines connected to selected ones of said cells which are contained in a row, a plurality of sum paths which extend through those cells which are assigned to the partial product bits of equal values which are to be added to each other, a plurality of carry paths which extend through those cells which are assigned to partial product bits of rising value which are to be added to each other, a plurality of full adders contained in each of said first plurality and said further plurality of cells, and said full adders adding a sum signal supplied by one of said plurality of sum paths and a carry signal supplied by one of said plurality of carry paths and the partial product bit assigned to said cell, all of said first and further plurality of cells each contain a first logic-link element which performs an AND-logic-link of a multiplicand bit to a multiplier bit, all of said first and said further plurality of cells contain shift register stages which are connected to the sum output and the carry output of each cell, further shift register stages connected to first and second input lines such that all the input lines which are connected to the cells of one row each contain a number of further shift register stages which corresponds to the number of preceding rows, digital signals obtained from the ends of said sum paths and said carry paths combined to form product bits, a first logic-link element in said cells so as to form a partial product bit, a plurality of full-adders in which the partial product bit is added to a sum signal and possibly to a carry signal are each located in two separate cells (Z23, Z33) which are located in different rows, the row of the cell (Z33) which contains the full-adder is located following the row of the cell (Z23) which contains said first logic-link element, and the output of said first logic-link element extends across a connection line (58) to an input of said full-adder which has a shift register stage (59) connected to its connection which serves to intermediately store the formed partial product bits.