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US4747068A Expired / Lapsed US ⏱️ 0.0 years remaining

Adaptive filter

Assignee: US Philips Corp
•
Filing: 1986-10-10
•
Granted: 1988-05-24
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Expires: 2006-10-10
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Abstract

Abstract In an adaptive filter a plurality of outputs (5, 7, 9, 11) of a delay circuit (3) are coupled via coefficient control circuits (21, 23, 25, 27) to a plurality of inputs (91, 93, 95, 97) of an adder circuit (89). The control signal inputs (29, 31, 33, 35) of the coefficient control circuits each receive a control signal via first integrators (37, 39, 41, 43) from first multiplier circuits (53, 55, 57, 59). A further output (85) of the delay circuit (3) controls a further input (87) of the adder circuit (89). The output signal from the adder circuit is controlled by a control circuit (121) which receives a control signal from a second multiplier circuit (103) via a second integrator (109) and a circuit having an exponential transfer function (113). A convergence behavior of the adaptive filter which is virtually independent of signal amplitudes is obtained by driving the integrators in such a way that the amplitude of their input signals are substantially independent of the amplitude of the signal at the input (1) of the filter (FIG. 1).

Inventors

  • 👤 Johannes O. Voorman
  • 👤 Louis J. van Mal

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-04 01:01
CPC Classifications
H; H03; H03H; H03H21/00; H03H21/0012

Claims Analysis

Total Claims: 2
Claim 1
Independent Claim 257 words
An adaptive filter comprising: a delay circuit having a plurality of outputs, for delaying an input signal to be filtered; a plurality of coefficient control circuits coupled to the outputs of said delay circuit; an adder circuit coupled at its inputs to the outputs of said coefficient control circuits; a plurality of first integrator circuits, the output of each being coupled to an input of a corresponding coefficient control circuit; a plurality of first multiplier circuits, the output of each being coupled to the input of a corresponding first integrtor circuit, and each having one of its inputs coupled to an output of said delay circuit; a correction signal generating circuit coupled at its output to an input of each first multiplier circuit; a second multiplier circuit coupled at one input to an output of said delay circuit and coupled at another input to the output of said correction signal generating circuit; a second integrator circuit coupled at its input to the output of said second multiplier circuit; a third multiplier circuit having a substantially exponential transfer characteristic, the input of said third multiplier circuit being coupled to the output of said second integrator circuit; and a control signal multiplier circuit for sending control signals from its output to an input of said correction signal generating circuit, said control signal multiplier circuit being coupled at one of its inputs to the output of said adder circuit, and said control signal multiplier circuit being coupled at another of its inputs to an output of said third multiplier circuit.
Claim 2
Dependent Claim 257 words
An adaptive filter comprising: a delay circuit having a plurality of outputs, for delaying an input signal to be filtered; a plurality of coefficient control circuits coupled to the outputs of said delay circuit; an adder circuit coupled at its inputs to the outputs of said coefficient control circuits; a plurality of first integrator circuits, the output of each being coupled to an input of a corresponding coefficient control circuit; a plurality of first multiplier circuits, the output of each being coupled to the input of a corresponding first integrtor circuit, and each having one of its inputs coupled to an output of said delay circuit; a correction signal generating circuit coupled at its output to an input of each first multiplier circuit; a second multiplier circuit coupled at one input to an output of said delay circuit and coupled at another input to the output of said correction signal generating circuit; a second integrator circuit coupled at its input to the output of said second multiplier circuit; a third multiplier circuit having a substantially exponential transfer characteristic, the input of said third multiplier circuit being coupled to the output of said second integrator circuit; and a control signal multiplier circuit for sending control signals from its output to an input of said correction signal generating circuit, said control signal multiplier circuit being coupled at one of its inputs to the output of said adder circuit, and said control signal multiplier circuit being coupled at another of its inputs to an output of said third multiplier circuit.

References Cited (Backward Citations)

US3597541A Cited
US3736414A Cited
US3781720A Cited
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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1991-05-24 1991-11-23 1992-05-24 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1995-05-24 1995-11-23 1996-05-24 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1999-05-24 1999-11-23 2000-05-24 $7700.00 Window Closed / Lapsed

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