Transversal filter equalizer for partial response channels

Claim 2

A transversal filter equalizer adapted to be connected to a source of partial response coded data wherein said data contains distortion, said equalizer filter comprising: a multi-tap delay line having tap points spaced one bit width apart; means for applying input signals in partial response coded form to one end of said delay line; adjustable gain means connected between said tap points and to either end of said delay line; means for summing the outputs of all the adjustable gain means; detection means having an output for converting partial response coded data obtained from said summing means to binary data; means for developing an error signal by re-creating a partial response coded signal from the output of said detection means and for comparing said re-created signal with the signal appearing at the input to said detection means; correlation means utilizing as one input said error signal; and means connecting the output of said correlation means to control said adjustable means connected to said tap points.

Claim 3

A transversal filter equalizer as set forth in claim 1 wherein said correlation means includes means for multiplying said error signal with a re-created precoded signal developed from the output of said detection means.

Claim 4

A transversal filter equalizer as set forth in claim 1 wherein said correlation means includes means for multiplying said error signal with the signal appearing directly on the tap points of said delay line in response to said input signals being applied to one end of said delay line.

Claim 5

A transversal filter equalizer for use with a partial response channel comprising: a multi-tap delay line having an input at one end thereof; means for supplying signals in partial response coded form to said input of said delay line; adjusted gain means connected to selected tap points of said delay line; summing means connected to the outputs of all of said adjusted gain means, the output of said summing means comprising the output of said delay line; the tap points of said delay line being spaced one bit width apart; detector means coupled to the output of said delay line to convert partial response coded data at its input into conventional binary data format; first means connected to the output of said detector means for converting the binary data from the detector into a precoded data format and second means connected to the output of said first connecting means for converting said precoded data format into a partial response coded format; error detection means for detecting the difference between the converted partial response coded data signal from the second converting means and the partial response coded data received from the output of said delay line to produce an error signal; correlation means utilizing the error signal to provide a plurality of control signals for controlling the settings of each of said adjustable gain means, whereby the control signal from the correlation means to said adjustable gain means approximates the inverse of the partial response characteristic 1-D2 wherein D z 1 in z-transform notation.

Claim 6

A transversal filter equalizer for use with a partial response channel comprising: a multi-tap delay line having an input at one end thereof; means for supplying signals in partial response coded form to said input of said delay line; adjusted gain means connected to selected tap points of said delay line; summing means connected to the outputs of all of said adjusted gain means, the output of said summing means comprising the output of said delay line; the tap points of said delay line being spaced one bit width apart; detector means coupled to the output of said delay line to convert partial response coded data at its input into conventional binary data format; first means connected to the output of said detector means for converting the binary data from the detector into a precoded data format and second means connected to the output of said first connecting means for converting said precoded data format into a partial response coded format; error detection means for detecting the difference between the converted partial response coded data signal from the second converting means and the partial response coded data received from the output of said delay line to produce an error signal; correlation means utilizing the error signal to provide a plurality of control signals for controlling the settings of each of said adjustable gain means, whereby the control signal from the correlation means to said adjustable gain means approximates the inverse of the partial response characteristic 1-D2 wherein D z 1 in z-transform notation.

Claim 7

A transversal filter equalizer as set forth in claim 4 wherein said correlation means comprises: M multipliers and M integrators, means for supplying the error signal and a signal derived from the directly received data to each multiplier, and means for supplying linear combinations of the mutliplier outputs to said integrators.

Claim 8

A transversal filter equalizer as set forth in claim 5 including a signal ambiguity resolving circuit which comprises: two level detection circuits for detecting whether the magnitude of a given signal appearing at the input of the detection means is greater than one-half of either the maximum positive or negative signal value of a normally received signal set; the output of said comparison circuits being fed respectively, to one input of an OR gate and an AND gate; the other input to said OR gate comprising the output of modulo-2 adder in the first converting circuit means; the output of said OR gate providing the other input to said AND gate, the output of said AND gate being the desired precoded signal set from said first converting circuit means.

Claim 9

A transversal filter equalizer as set forth in claim 5 wherein said delay line comprises M tap points; M adjustable gain control means located between said M tap points and the output of said delay line; said correlation circuits means comprising said M integrators and M multipliers wherein one input to each multiplier emanates from said error signal (e) generating means and the other input is the precoded signal (b) from said second converting circuit means; means connecting the output of at least one of said multipliers to the input to each of said integration circuit means; and means connecting the output of each said integrator to control the gain setting of said adjustable gain means.

Claim 10

A transversal filter equalizer as set forth in claim 7 wherein the output qi from the ith multiplier is defined as the product of bn. 1n i; where i < or = 0, and as the product of bn i. 1n; where i >0, and wherein the input to the ith integrator is defined as the summation of qi + qi 2 + qi 4 ......... qi 2j where j < or = (i + F)/2; where F is the number of taps on the delay line ahead of the principal tap.

Claim 11

A transversal filter equalizer as set forth in claim 7 wherein the output qi from the ith multiplier is defined as the product of en . xn i 2 and wherein the input to the ith integrator is defined by the summation of: qi + 2qi 2 + 3qi 4 + 4qi 6 .... jqi 2j 2 where j < or = (i + F + 2)/2 and where there are F + 2 taps ahead of the pRincipal tap.

Claim 12

A transversal filter equalizer as set forth in claim 5 wherein said delay line comprises N tap points separated by one bit width; M adjustable gain control means conntected to the last M tap points of said delay line relative to the input end of said delay line wherein M N-2; means connecting the output of said adjustable gain means to the output of said delay line; means for supplying the generated error signal as one input to each of said M multipliers; means for supplying to the ith multiplier the signal appearing on the ith tap point of said delay line, means connecting the output of at least the ith multiplier to the ith integrator with an input weighting of 1, and means connecting the output of the ith integrator of said M integrators to the ith adjustable gain control means which in turn adjusts the gain of the (i+2)th tap of said delay line.