Process for preparing a charge coupled device with charge transfer direction biasing implants

Claim 1

A process of fabricating at a region of a first conductivity type in a semiconductive substrate a two phase or virtual phase charge coupled device having at least one set of gate electrodes, wherein initially a conductive gate electrode forming layer used to form said one set of gate electrodes overlies said region and an interface barrier means limits charge conduction therebetween, comprising (i) implanting a dopant in said semiconductive substrate region within laterally spaced local zones through said gate electrode forming layer, (ii) forming spaced barriers each having a first barrier segment overlying alternate spaced local zones and a second contiguous barrier segment overlying alternate intervals between spaced local zones, (iii) selectively removing said conductive gate electrode forming layer in areas not protected by said spaced barrier to form said one set of gate electrodes, and (iv) locating a second set of gate electrodes between adjacent electrodes of said one set, characterized in that said one set of gate electrodes are formed in edge alignment with said spaced zones by the steps of (a) locating on said gate electrode forming layer a coating of a barrier forming layer which can be converted to a removal resistant form, (b) forming over said barrier forming layer a pattern forming layer and removing portions of said pattern forming layer to produce a series of laterally spaced pattern layer segments and openings therebetween, (c) through the openings, said barrier forming layer, and said gate electrode forming layer implanting said dopant in said semiconductive substrate region within said laterally spaced local zones, (d) removing said barrier forming layer exposed by alternate of the openings, (e) converting that portion of said barrier forming layer exposed by remaining openings to a removal resistant form to produce said first barrier segments overlying alternate spaced local zones, and (f) removing the pattern layer segments and portions of the barrier forming layer corresponding to alternate pattern layer segments to form said second barrier segments contiguous with said first barrier segments and overlying alternate intervals between said spaced local zones, each of steps (a) trough (f) being performed at a temperture below that required for lattice or intesticial migration in said semiconductive substrate.