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US4745573A
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Programmable clock generator
Assignee: Symbolics Inc
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Filing: 1986-04-11
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Granted: 1988-05-17
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Expires: 2006-04-11
Abstract
Abstract A programmable clock generator includes programmable logic arrays implementing a shift register and control circuits elements connected between the inputs and outputs of the shift register elements and responsive to a code applied thereto for skipping preselected shift register elements during shifting. At least one JK flip-flop is receptive of timing signals from non-skipped shift register elements at the J and K inputs thereof to produce a clock signal at the output thereof.
Inventors
- 👤 Ronald J. Lebel
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 07:39
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/04; G06F1/08
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
117 words
A programmable clock generator comprising programmable logic array means including: a shift register having a plurality of register elements, each shift register element having an input for receiving a timing signal and an output for producing a timing signal during shifting and control means connected to selected ones of said inputs and outputs of the shift register elements and responsive to a code applied thereto for effecting the skipping of preselected shift register elements during shifting; and at least one JK flip-flop receptive of timing signals from the outputs of non-skipped shift register elements at the J and K inputs thereof to produce a clock signal at the output thereof having desired characteristics represented by said code.
Claim 2
Dependent Claim
117 words
A programmable clock generator comprising programmable logic array means including: a shift register having a plurality of register elements, each shift register element having an input for receiving a timing signal and an output for producing a timing signal during shifting and control means connected to selected ones of said inputs and outputs of the shift register elements and responsive to a code applied thereto for effecting the skipping of preselected shift register elements during shifting; and at least one JK flip-flop receptive of timing signals from the outputs of non-skipped shift register elements at the J and K inputs thereof to produce a clock signal at the output thereof having desired characteristics represented by said code.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-05-17 | 1991-11-16 | 1992-05-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-05-17 | 1995-11-16 | 1996-05-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-05-17 | 1999-11-16 | 2000-05-17 | $7700.00 | Window Closed / Lapsed |