Patent US4745395A successfully refreshed from Google Patents.
US4745395A
Expired / Lapsed
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Precision current rectifier for rectifying input current
Assignee: General Datacomm Inc
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Filing: 1987-01-28
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Granted: 1988-05-17
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Expires: 2007-01-28
Abstract
Abstract A current rectifier is provided and generally comprises: a p-channel transistor and an n-channel transistor having common gates connected to ground and common sources connected to an input current I in ; and a first current mirror with its input connected to the drain of the n-channel transistor, and its output connected to the drain of the p-channel transistor. The current rectifier preferably also includes a second current mirror with the drain of the p-channel transistor as an input to the second current mirror and the rectified output current I out as an output of the second current mirror. If an offset to the rectified current is desired, a third current mirror having a bias or offset current as an input and the output of the second current mirror as an output may be included.
Inventors
- 👤 Jeffrey I. Robinson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 13:07
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/12; H03M1/34; H03M1/38; H03M1/44; H03M1/447; H02; H02M; H02M7/00; H02M7/02; H02M7/04; H02M7/12; H02M7/21; H02M7/217
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
126 words
An apparatus for rectifying an input current, comprising: (a) a p-channel transistor and an n-channel transistor having common gates connected to ground and common sources connected to an input current I in ; (b) a first current mirror with its input connected to the drain of said n-channel transistor, and its output connected to the drain of said p-channel transistor; (c) a second current mirror with the drain of said p-channel transistor as an input and a rectified output current I out as an output; and (d) a third current mirror having a bias current I ref as an input and the output of said second current mirror as an output, wherein the rectified output current is thereby offset and equals I out -I ref .
Claim 2
Independent Claim
126 words
An apparatus for rectifying an input current, comprising: (a) a p-channel transistor and an n-channel transistor having common gates connected to ground and common sources connected to an input current I in ; (b) a first current mirror with its input connected to the drain of said n-channel transistor, and its output connected to the drain of said p-channel transistor; (c) a second current mirror with the drain of said p-channel transistor as an input and a rectified output current I out as an output; and (d) a third current mirror having a bias current I ref as an input and the output of said second current mirror as an output, wherein the rectified output current is thereby offset and equals I out -I ref .
Claim 3
Dependent Claim
21 words
An apparatus according to claim 1, wherein: said first and second current mirrors each comprise a four transistor CMOS current mirror.
Claim 4
Dependent Claim
22 words
An apparatus according to claim 1, wherein: said first, second, and third current mirrors each comprise a four transistor CMOS current mirror.
Claim 5
Dependent Claim
267 words
In an apparatus for the analog to digital conversion of a signal having a plurality of stages for performing the conversion algorithm I out =2|I in |-I ref , wherein I in is the current at the input of a particular stage, I out is the current at the output of that stage which becomes the I in to the next stage, and I ref is a chosen reference current, each stage comprising a current rectifier, and a first current mirror having said I ref as an input and said I out as an output, wherein a bit of information is obtained from the direction of the current flow of each I in , the bit obtained from each stage together forming a Gray code output word, a current rectifier, comprising: (a) a p-channel transistor and an n-channel transistor having common gates connected to ground and common sources connected to an input current I in ; (b) a second current mirror with its input connected to the drain of said n-channel transistor, and its output connected to the drain of said p-channel transistor; and (c) a third current mirror with the drain of said p-channel transistor as an input and the rectified output current I out as an output, wherein said third current mirror has at least one transistor on its input side and at least one transistor on its output side, and the transistors on the output side of said third current mirror are twice the width of the corresponding transistors on the input side of said current mirror, to provide a rectified gain of two.
Claim 6
Dependent Claim
267 words
In an apparatus for the analog to digital conversion of a signal having a plurality of stages for performing the conversion algorithm I out =2|I in |-I ref , wherein I in is the current at the input of a particular stage, I out is the current at the output of that stage which becomes the I in to the next stage, and I ref is a chosen reference current, each stage comprising a current rectifier, and a first current mirror having said I ref as an input and said I out as an output, wherein a bit of information is obtained from the direction of the current flow of each I in , the bit obtained from each stage together forming a Gray code output word, a current rectifier, comprising: (a) a p-channel transistor and an n-channel transistor having common gates connected to ground and common sources connected to an input current I in ; (b) a second current mirror with its input connected to the drain of said n-channel transistor, and its output connected to the drain of said p-channel transistor; and (c) a third current mirror with the drain of said p-channel transistor as an input and the rectified output current I out as an output, wherein said third current mirror has at least one transistor on its input side and at least one transistor on its output side, and the transistors on the output side of said third current mirror are twice the width of the corresponding transistors on the input side of said current mirror, to provide a rectified gain of two.
References Cited (Backward Citations)
US4445053A
Cited
US4495425A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-05-17 | 1991-11-16 | 1992-05-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-05-17 | 1995-11-16 | 1996-05-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-05-17 | 1999-11-16 | 2000-05-17 | $7700.00 | Window Closed / Lapsed |