Patent US4745305A successfully refreshed from Google Patents.
US4745305A
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Common cell I/O interface circuit
Assignee: MagnaChip Semiconductor Ltd
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Filing: 1985-09-23
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Granted: 1988-05-17
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Expires: 2005-09-23
Abstract
Abstract A common cell for use as an input/output circuit in a CMOS integrated circuit having a P-channel transistor structure having a plurality of individual P-channel transistors, an N-channel transistor structure having a plurality of individual N-channel transistors and an I/O pad. The sources, drains and gates of the individual P-channel and N-channel transistors are connected to terminals. The various terminals and the I/O pad may be selectively connected in various ways to form various input/output circuits, as desired.
Inventors
- 👤 Harold S. Crafts
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 08:31
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/90; H10D84/998; H03; H03K; H03K19/00; H03K19/0175; H03K19/0185; H03K19/018507; H03K19/018521; H03K19/018585; H03K19/018592; H03K19/02; H03K19/173; H03K19/1733; H03K19/1735
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
193 words
A common cell for use as an input/output circuit in an integrated circuit comprising: an I/O pad; a P-channel transistor structure having a plurality of individual P-channel transistors; an N-channel transistor structure having a plurality of individual N-channel transistors; a Vdd terminal connected to the sources of the individual P-channel transistors of the P-channel transistor structure; a P-channel drain terminal connected to the drains of the individual P-channel transistors of the P-channel transistor structure; a plurality of P-channel gate terminals, each connected to one of the gates of the individual P-channel transistors of the P-channel transistor structure; a Vss terminal connected to the sources of the individual N-channel transistors of the N-channel transistor structure; an N-channel drain terminal connected to the drains of the individual N-channel transistors of the N-channel transistor structure and to said P-channel drain terminal; and a plurality of N-channel gate terminals, each connected to one of the gates of the individual N-channel transistors of the N-channel transistor structure; said I/O pad, P-channel drain terminal, P-channel gate terminals, N-channel drain terminal, and N-channel gate terminals being selectively connected, as desired, to form selected input/output circuit configurations having electrostatic discharge protection.
Claim 2
Dependent Claim
193 words
A common cell for use as an input/output circuit in an integrated circuit comprising: an I/O pad; a P-channel transistor structure having a plurality of individual P-channel transistors; an N-channel transistor structure having a plurality of individual N-channel transistors; a Vdd terminal connected to the sources of the individual P-channel transistors of the P-channel transistor structure; a P-channel drain terminal connected to the drains of the individual P-channel transistors of the P-channel transistor structure; a plurality of P-channel gate terminals, each connected to one of the gates of the individual P-channel transistors of the P-channel transistor structure; a Vss terminal connected to the sources of the individual N-channel transistors of the N-channel transistor structure; an N-channel drain terminal connected to the drains of the individual N-channel transistors of the N-channel transistor structure and to said P-channel drain terminal; and a plurality of N-channel gate terminals, each connected to one of the gates of the individual N-channel transistors of the N-channel transistor structure; said I/O pad, P-channel drain terminal, P-channel gate terminals, N-channel drain terminal, and N-channel gate terminals being selectively connected, as desired, to form selected input/output circuit configurations having electrostatic discharge protection.
Claim 3
Dependent Claim
69 words
The common cell of claim 1 wherein: the P-channel drain terminal is connected to the I/O pad; the N-channel drain terminal is connected to the I/O pad; the P-channel gate terminals are commonly connected to a P-channel output circuit of the integrated circuit for receiving P-channel output signals; the N-channel gate terminals are commonly connected to an N-channel output circuit of the integrated circuit for receiving N-channel output signals.
Claim 4
Dependent Claim
55 words
The common cell of claim 2 further comprising an input terminal connected to the I/O pad, said input terminal being connectable to an input circuit of the integrated circuit wherein input signals imposed on said I/O pad may be transmitted to said input terminal for being inputted into the input circuit of the integrated circuit.
Claim 5
Dependent Claim
65 words
The common cell of claim 1 wherein the P-channel drain terminal is connected to the I/O pad, the N-channel drain terminal is connected to the I/O pad, and the P-channel gate terminals and the N-channel gate terminals are tied together to a common output terminal for receiving output signals from an output circuit of the integrated circuit for placing output signals on the I/O pad.
Claim 6
Dependent Claim
67 words
The common cell of claim 1 wherein the P-channel drain terminal is connected to the I/O pad, the N-channel drain terminal is connected to the I/O pad, the P-channel gate terminals are commonly connected to said Vdd terminal and the N-channel gate terminals are commonly connected to an output terminal for connection with an output circuit in the integrated circuit forming a bidirectional open drain output circuit.
Claim 7
Dependent Claim
53 words
The common cell of claim 5 further comprising an input terminal connected to said I/O pad, said input terminal being arranged for connection to an input circuit in the integrated circuit wherein input signals placed on said I/O pad are transmitted by said input terminal to the input circuit of the integrated circuit.
Claim 8
Dependent Claim
16 words
The common cell of claim 2 further comprising a reference connected to said P-channel gate terminal.
Claim 9
Dependent Claim
13 words
The common cell of claim 7 wherein said reference is a current mirror.
Claim 10
Dependent Claim
16 words
The common cell of claim 2 further comprising a reference connected to said N-channel gate terminal.
Claim 11
Dependent Claim
13 words
The common cell of claim 9 wherein said reference is a current mirror.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-05-17 | 1991-11-16 | 1992-05-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-05-17 | 1995-11-16 | 1996-05-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-05-17 | 1999-11-16 | 2000-05-17 | $7700.00 | Window Closed / Lapsed |