US4745085A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of making I2 L heterostructure bipolar transistors
Assignee: Siemens Corporate Research and Support Inc
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Filing: 1986-12-01
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Granted: 1988-05-17
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Expires: 2006-12-01
Abstract
Abstract A process of making an integrated injection logic (I 2 L) semiconductor structure is disclosed which is particularly advantageous for implementation in a group III-V compound semiconductor such as gallium arsenide. By use of "regrowth" techniques, the base region of the lateral transistor is made extremely thin (less than one-tenth micron). Utilization of a Schottky collector in a vertical transistor simplifies the structure.
Inventors
- 👤 Chan-Long Shieh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 19:14
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0112; H10D84/0116; H10D84/02; H10D84/03; H10D84/038; H10P; H10P14/00; H10P14/20; H10P14/27; H10P14/271; H10P14/29; H10P14/2901; H10P14/2907; H10P14/2911; H10P14/32; H10P14/3202; H10P14/3214; H10P14/3221; H10P14/3242; H10P14/3244; H10P14/3251; H10P14/3254; H10P14/34; H10P14/3402; H10P14/3414; H10P14/3421; H10D84/05; Y; Y10; Y10S; Y10S148/00; Y10S148/011; Y10S438/00; Y10S438/936
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
242 words
A method of fabricating transistors for integrated injection logic, said method comprising the steps of: (a) growing, on one side of a substrate of III-V compound semiconductor material having a first conductivity type, an epitaxial first layer of the same, first conductivity type; (b) growing an epitaxial second layer on said first layer, said second layer having a second conductivity type opposite to that of said first conductivity type; (c) depositing an insulating third layer on said second layer; (d) etching a first opening in said second and third layers to the depth of said first layer; (e) growing an epitaxial fourth layer of semi-insulating polycrystalline material of said second conductivity type on said fourth layer in said first opening; (f) growing an epitaxial fifth layer of semi-insulating polycrystalline material of said second conductivity type on said fourth layer in said first opening; (g) etching a second opening in said third, fourth and fifth layers to the depth of said second layer; (h) depositing an ohmic first contact on said fifth layer over said first opening, thereby contacting the emitter of a lateral transistor and depositing an ohmic second contact on said second layer through said second opening, thereby contacting the collector of the lateral transistor; and (i) depositing an ohmic third contact on the opposite side of said substrate, thereby contacting the base of said lateral transistor; whereby the base region of said lateral transistor is formed by said fourth layer.
Claim 2
Independent Claim
242 words
A method of fabricating transistors for integrated injection logic, said method comprising the steps of: (a) growing, on one side of a substrate of III-V compound semiconductor material having a first conductivity type, an epitaxial first layer of the same, first conductivity type; (b) growing an epitaxial second layer on said first layer, said second layer having a second conductivity type opposite to that of said first conductivity type; (c) depositing an insulating third layer on said second layer; (d) etching a first opening in said second and third layers to the depth of said first layer; (e) growing an epitaxial fourth layer of semi-insulating polycrystalline material of said second conductivity type on said fourth layer in said first opening; (f) growing an epitaxial fifth layer of semi-insulating polycrystalline material of said second conductivity type on said fourth layer in said first opening; (g) etching a second opening in said third, fourth and fifth layers to the depth of said second layer; (h) depositing an ohmic first contact on said fifth layer over said first opening, thereby contacting the emitter of a lateral transistor and depositing an ohmic second contact on said second layer through said second opening, thereby contacting the collector of the lateral transistor; and (i) depositing an ohmic third contact on the opposite side of said substrate, thereby contacting the base of said lateral transistor; whereby the base region of said lateral transistor is formed by said fourth layer.
Claim 3
Dependent Claim
52 words
The method defined in claim 1, further comprising the steps of: (j) etching a third opening in said third, fourth and fifth layers to the depth of said second layer; (k) depositing a Schottky fourth contact in said third opening on said second layer, thereby forming the collector of a vertical transistor.
Claim 4
Dependent Claim
16 words
The method defined in claim 1, wherein said fourth layer is less than one-tenth micron thick.
Claim 5
Dependent Claim
16 words
The method defined in claim 1, wherein said fourth layer is formed with a graded bandgap.
Claim 6
Dependent Claim
22 words
The method defined in claim 1, wherein said first conductivity type is negative (n) and said second conductivity type is positive (p).
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-05-17 | 1991-11-16 | 1992-05-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-05-17 | 1995-11-16 | 1996-05-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-05-17 | 1999-11-16 | 2000-05-17 | $7700.00 | Window Closed / Lapsed |