Patent US4744054A successfully refreshed from Google Patents.
US4744054A
Expired / Lapsed
US
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Semiconductor device with a memory circuit
Assignee: NEC Electronics Corp
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Filing: 1985-02-15
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Granted: 1988-05-10
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Expires: 2005-02-15
Abstract
Abstract A semiconductor device has a first ROM and a second ROM on a single semiconductor chip. To write information in the first ROM, a contact mask pattern is used by which wirings are formed on the chip, while information is written in the second ROM when memory transistors are formed on the chip. The first ROM stores the non-commonly used information of the program to be stored, or a specific user supplied program, and the second ROM stores predetermined and commonly used information of the program to be stored. Thus, a semiconductor device having a fixed memory in which a large capacity of information is stored can be provided to a user within a short period of time.
Inventors
- 👤 Kazuhide Kawata
- 👤 Hiroyuki Suzuki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 08:58
CPC Classifications
G; G11; G11C; G11C17/00; G11C17/08; G11C17/10; G11C17/12
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
91 words
A single-chip microcomputer device, comprising; semiconductor memory means provided on said chip, said memory means having an address space divided into first and second sections, said first section comprising a user area and said second section comprising a system area; said first section being comprised of a first ROM memory of the type which is programmed when wiring layers are formed on said chip, and said second section being comprised of a second ROM memory of the type in which information is written when memory cells are formed on said chip.
Claim 2
Dependent Claim
91 words
A single-chip microcomputer device, comprising; semiconductor memory means provided on said chip, said memory means having an address space divided into first and second sections, said first section comprising a user area and said second section comprising a system area; said first section being comprised of a first ROM memory of the type which is programmed when wiring layers are formed on said chip, and said second section being comprised of a second ROM memory of the type in which information is written when memory cells are formed on said chip.
Claim 3
Dependent Claim
39 words
A microcomputer device as claimed in claim 1, wherein information to be stored in said first ROM comprises at least a user program, and wherein information to be stored in said second ROM comprises at least a system program.
Claim 4
Dependent Claim
36 words
A microcomputer device as claimed in claim 2, wherein said system program is prerecorded during initial manufacture of said microcomputer device, and wherein said user program is subsequently defined by further customized processing of said chip.
Claim 5
Dependent Claim
104 words
A single chip microcomputer of the type incorporating a read only memory, comprising; first and second read only memory sections, said first section comprising a user area comprised of a ROM of the type in which information is written according to whether a preformed transistor at a cross location of a word line and a bit line is connected to said bit line, and wherein said second section comprises a system memory area comprised of a ROM of the type in which information is written according to whether a transistor is formed at a cross location of a word line and a bit line.
Claim 6
Dependent Claim
104 words
A single chip microcomputer of the type incorporating a read only memory, comprising; first and second read only memory sections, said first section comprising a user area comprised of a ROM of the type in which information is written according to whether a preformed transistor at a cross location of a word line and a bit line is connected to said bit line, and wherein said second section comprises a system memory area comprised of a ROM of the type in which information is written according to whether a transistor is formed at a cross location of a word line and a bit line.
Claim 7
Dependent Claim
133 words
A single chip microcomputer having an on-board read only memory, comprising; first and second ROM memories within the address space of said microcomputer and formed on said chip, said first ROM memory defining a user memory area and being of the type wherein information is written in accordance with whether or not a transistor formed at a location where a word line crosses a bit line is connected to said bit line, and wherein said second ROM memory defines a system memory area and comprises a memory of the type having first type transistors activated in response to an address signal applied to a word line and second type transistors non-activated in response to an address signal, said first and second type transistors being selectively formed according to the information to be stored.
Claim 8
Dependent Claim
133 words
A single chip microcomputer having an on-board read only memory, comprising; first and second ROM memories within the address space of said microcomputer and formed on said chip, said first ROM memory defining a user memory area and being of the type wherein information is written in accordance with whether or not a transistor formed at a location where a word line crosses a bit line is connected to said bit line, and wherein said second ROM memory defines a system memory area and comprises a memory of the type having first type transistors activated in response to an address signal applied to a word line and second type transistors non-activated in response to an address signal, said first and second type transistors being selectively formed according to the information to be stored.
Claim 9
Dependent Claim
98 words
A single chip microcomputer device, comprising; read only memory means formed on said chip and addressable by said microcomputer; said read only memory means comprising a first memory section of the type in which information storage is effected by introducing an impurity into selected portions of a semiconductor substrate, said first memory section comprising a system memory area, and a second memory section of the type in which information is stored according to a mask pattern via which source regions of selected transistors are connected to drain regions thereof, said second memory section comprising a user memory area.
Claim 10
Dependent Claim
98 words
A single chip microcomputer device, comprising; read only memory means formed on said chip and addressable by said microcomputer; said read only memory means comprising a first memory section of the type in which information storage is effected by introducing an impurity into selected portions of a semiconductor substrate, said first memory section comprising a system memory area, and a second memory section of the type in which information is stored according to a mask pattern via which source regions of selected transistors are connected to drain regions thereof, said second memory section comprising a user memory area.
Claim 11
Dependent Claim
96 words
A single chip microcomputer having an on-board read only memory, comprising; first and second ROM memories within the address space of said microcomputer and formed on said chip, said first ROM memory defining a user memory area and being of the type wherein information may be written by controlling the connectivity of pre-formed transistors on a semiconductor substrate, and wherein said second ROM memory defines a system memory area and comprises a memory of the type wherein transistors in a memory cell array are formed or not formed according to the desired content of said memory.
Claim 12
Dependent Claim
96 words
A single chip microcomputer having an on-board read only memory, comprising; first and second ROM memories within the address space of said microcomputer and formed on said chip, said first ROM memory defining a user memory area and being of the type wherein information may be written by controlling the connectivity of pre-formed transistors on a semiconductor substrate, and wherein said second ROM memory defines a system memory area and comprises a memory of the type wherein transistors in a memory cell array are formed or not formed according to the desired content of said memory.
References Cited (Backward Citations)
US4057787A
Cited
US4059826A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-05-10 | 1991-11-09 | 1992-05-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-05-10 | 1995-11-09 | 1996-05-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-05-10 | 1999-11-09 | 2000-05-10 | $7700.00 | Window Closed / Lapsed |