Insulated-gate semiconductor device with low on-resistance

Claim 2

An insulated-gate semiconductor device with low on-resistance, comprising: (a) an insulated-gate field-effect transistor including, in successive arrangement, a drain region, a drift region, a base region and a channel region; said base region being of one conductivity type and said drain and drift regions being of the opposite conductivity type; and further including a plurality of external contacts for connection of said device into a circuit; a drain electrode attached to said drain region and ohmically connected to a first one of said external contacts, a source electrode attached to said base region and ohmically connected to a second one of said external contacts and a gate electrode ohmically connected to a third one of said external contacts and insulatingly spaced from said channel region to determine the conductive state of said channel region in response to bias voltage thereon; (b) a carrier injection region adjoining said drift region and being of the one conductivity type so as to form a P-N junction with said drift region, said carrier injection region being free of ohmic connections to said external contacts; and (c) bias means connected to said carrier injection region and effective during the on state of the semiconductor device for forward biasing said P-N junction by an amount sufficient to induce injection of one type carriers from said carrier injection region, across said P-N junction, and into said drift region, thereby reducing the on-resistance of said drift region and of the semiconductor device.

Claim 3

The semiconductor device of claim 1 wherein said bias means comprises: (a) an injection region electrode contacting said carrier injection region and spaced from said drift region; (b) a second channel region adjoining said carrier injection region and, when in a conductive state, completing a current path of the opposite conductivity type extending from said drift region to said injection region electrode; and (c) a second gate electrode insulatingly spaced from said second channel region so as to be effective to determine the conductive state of said second channel region in response to a bias thereon.

Claim 4

An insulated-gate semiconductor device with low on-resistance, comprising: (a) an insulated-gate field-effect transistor including, in successive arrangement, a drain region, a drift region, a base region and a first channel region; said base region being of one conductivity type and said drain and drift regions being of the opposite conductivity type; and further including a drain electrode attached to said drain region, a source electrode attached to said base region, and a first gate insulatingly spaced from said channel region to determine the conductive state of said channel region in response to a bias voltage thereon; (b) a carrier injection region adjoining said drift region and being of the one conductivity type so as to form a P-n junction with said drift region, said carrier injection region being free of ohmic connections to said source electrode and to said gate electrode; and (c) bias means connected to said carrier injection region and effective during the on state of the semiconductor device for forward biasing said P-N junction by an amount sufficient to induce injection of one type carriers from said carrier injection region, across said P-N junction, and into said drift region, thereby reducing the on-resistance of said drift region and of the semiconductor device wherein said bias means comprises: (1) an injection region electrode contacting said carrier injection region and spaced from said drift region; (2) a second channel region adjoining said carrier injection region and, when in a conductive state, completing a current path of the opposite conductivity type extending from said drift region to said injection region electrode; (3) a second gate electrode insulatingly spaced from said second channel region so as to be effective to determine the conductive state of said second channel region in response to a bias thereon; and (4) a region of the opposite conductivity type spaced from said drift region and adjoining said carrier injection region and being electrically interposed between said second channel region and said injection region electrode so as to be in said current path from said drift region to said injection region electrode.

Claim 5

An insulated-gate semiconductor device with low on-resistance, comprising: (a) an insulated-gate field-effect transistor including, in successive arrangement, a drain region, a drift region, a base region and a first channel region; said base region being of one conductivity type and said drain and drift regions being of the opposite conductivity type; and further including a drain electrode attached to said drain region, a source electrode attached to said base region, and a first gate insulatingly spaced from said channel region to determine the conductive state of said channel region in response to a bias voltage thereon; (b) a carrier injection region adjoining said drift region and being of the one conductivity type so as to form a P-n junction with said drift region, said carrier injection region being free of ohmic connections to said source electrode and to said gate electrode; and (c) bias means connected to said carrier injection region and effective during the on state of the semiconductor device for forward biasing said P-N junction by an amount sufficient to induce injection of one type carriers from said carrier injection region, across said P-N junction, and into said drift region, thereby reducing the on-resistance of said drift region and of the semiconductor device wherein said bias means comprises: (1) an injection region electrode contacting said carrier injection region and spaced from said drift region; (2) a second channel region adjoining said carrier injection region and, when in a conductive state, completing a current path of the opposite conductivity type extending from said drift region to said injection region electrode; (3) a second gate electrode insulatingly spaced from said second channel region so as to be effective to determine the conductive state of said second channel region in response to a bias thereon; and (4) a region of the opposite conductivity type spaced from said drift region and adjoining said carrier injection region and being electrically interposed between said second channel region and said injection region electrode so as to be in said current path from said drift region to said injection region electrode.

Claim 6

The semiconductor device of claim 2 wherein said first mentioned channel region and said second channel region each comprise semiconductor material of the one conductivity type, whereby the semiconductor device exhibits normally-off performance.

Claim 7

The semiconductor device of claim 2 wherein said first mentioned gate electrode and said second gate electrode are ohmically connected together, whereby a single control signal is effective to control the conductive state of the semiconductor device.

Claim 8

An insulated-gate semiconductor device with low on-resistance, comprising: (a) an insulated-gate field-effect transistor including, in successive arrangement, a drain region, a drift region, a base region and a channel region; said base region being of one conductivity type and said drain and drift regions being of the opposite conductivity type; and further including a drain electrode attached to said drain region, a source electrode attached to said base region, and a gate electrode insulatingly spaced from said channel region to determine the conductive state of said channel region in response to a bias voltage thereon; (b) a carrier injection region adjoining said drift region and being of the one conductivity type so as to form a P-N junction with said drift region; and (c) bias means connected to said carrier injection region and effective during the on state of the semiconductor device for forward biasing said P-N junction by an amount sufficient to induce injection of one type conductivity carriers from said carrier injection region, across said P-N junction, and into said drift region, thereby reducing the on-resistance of said drift region and of the semiconductor device, whereby said bias means comprises: (1) a first highly-doped region of the one conductivity type adjoining said carrier injection region; (2) a second highly-doped region of the opposite conductivity type spaced from said drift region and adjoining both said carrier injection region and said first highly-doped region, said first and second highly-doped regions being doped sufficiently high in concentration as to form a tunnel junction therebetween; (3) a second channel region adjoining said carrier injection region and, when said second channel region is in a conductive state, completing a current path of the opposite conductivity type extending from said drift region to said second highly-doped region; and (4) a second gate electrode insulatingly spaced from said second channel region so as to be effective to determine the conductive state of said second channel region in response to a bias voltage.

Claim 9

An insulated-gate semiconductor device with low on-resistance, comprising: (a) an insulated-gate field-effect transistor including, in successive arrangement, a drain region, a drift region, a base region and a channel region; said base region being of one conductivity type and said drain and drift regions being of the opposite conductivity type; and further including a drain electrode attached to said drain region, a source electrode attached to said base region, and a gate electrode insulatingly spaced from said channel region to determine the conductive state of said channel region in response to a bias voltage thereon; (b) a carrier injection region adjoining said drift region and being of the one conductivity type so as to form a P-N junction with said drift region; and (c) bias means connected to said carrier injection region and effective during the on state of the semiconductor device for forward biasing said P-N junction by an amount sufficient to induce injection of one type conductivity carriers from said carrier injection region, across said P-N junction, and into said drift region, thereby reducing the on-resistance of said drift region and of the semiconductor device, whereby said bias means comprises: (1) a first highly-doped region of the one conductivity type adjoining said carrier injection region; (2) a second highly-doped region of the opposite conductivity type spaced from said drift region and adjoining both said carrier injection region and said first highly-doped region, said first and second highly-doped regions being doped sufficiently high in concentration as to form a tunnel junction therebetween; (3) a second channel region adjoining said carrier injection region and, when said second channel region is in a conductive state, completing a current path of the opposite conductivity type extending from said drift region to said second highly-doped region; and (4) a second gate electrode insulatingly spaced from said second channel region so as to be effective to determine the conductive state of said second channel region in response to a bias voltage.

Claim 10

The semiconductor device of claim 6 wherein said first mentioned channel region and said second channel region each comprise semiconductor material of the one conductivity type, whereby the semiconductor device exhibits normally-off performance.

Claim 11

The semiconductor device of claim 6 wherein said first mentioned gate electrode and said second gate electrode are ohmically connected together, whereby a single control singal is effective to control the conductive state of the semiconductor device.

Claim 12

An insulated-gate semiconductor device with low on-resistance, comprising: (a) an insulated-gate field-effect transistor including, in successive arrangement, a drain region, a drift region, a base region and a first channel region; said base region being of one conductivity type and said drain and drift regions being of the opposite conductivity type; and further including a drain electrode attached to said drain region, a source electrode attached to said base region, and a first gate electrode insulatingly spaced from said first channel region to determine the conductive state of said first channel region in response to a bias voltage thereon; (b) a carrier injection region adjoining said drift region and being of the one conductivity type so as to form a P-N junction with said drift region; and (c) bias means connected to said carrier injection region and effective during the on state of the semiconductor device for forward biasing said P-N junction by an amount sufficient to induce injection of one type carriers from said carrier injection region, across said P-N junction, and into said drift region, thereby reducing the on-resistance of said drift region and of the semiconductor device, wherein said bias means comprises: (1) a further region of the one conductivity type adjoining said drift region and spaced from said carrier injection region; (2) a further region electrode adjoining said further region and being ohmically connected to said carrier injection region, but being free of ohmic connections to said source electrode; (3) a second channel region adjoining said further region and, when in a conductive state, completing a current path of the opposite conductivity type extending from said drift region to said further region electrode; and (4) a second gate electrode insulatingly spaced from said second channel region so as to be effective to determine the conductive state of said second channel region in response to a bias voltage thereon.

Claim 13

An insulated-gate semiconductor device with low on-resistance, comprising: (a) an insulated-gate field-effect transistor including, in successive arrangement, a drain region, a drift region, a base region and a first channel region; said base region being of one conductivity type and said drain and drift regions being of the opposite conductivity type; and further including a drain electrode attached to said drain region, a source electrode attached to said base region, and a first gate electrode insulatingly spaced from said first channel region to determine the conductive state of said first channel region in response to a bias voltage thereon; (b) a carrier injection region adjoining said drift region and being of the one conductivity type so as to form a P-N junction with said drift region; and (c) bias means connected to said carrier injection region and effective during the on state of the semiconductor device for forward biasing said P-N junction by an amount sufficient to induce injection of one type carriers from said carrier injection region, across said P-N junction, and into said drift region, thereby reducing the on-resistance of said drift region and of the semiconductor device, wherein said bias means comprises: (1) a further region of the one conductivity type adjoining said drift region and spaced from said carrier injection region; (2) a further region electrode adjoining said further region and being ohmically connected to said carrier injection region, but being free of ohmic connections to said source electrode; (3) a second channel region adjoining said further region and, when in a conductive state, completing a current path of the opposite conductivity type extending from said drift region to said further region electrode; and (4) a second gate electrode insulatingly spaced from said second channel region so as to be effective to determine the conductive state of said second channel region in response to a bias voltage thereon.

Claim 14

The semiconductor device of claim 9 wherein said first channel region and said second channel region each comprise semiconductor material of the one conductivity type, whereby the semiconductor device attains normally-off performance.

Claim 15

The semiconductor device of claim 9 wherein said first gate electrode and said second gate electrode are ohmically connected together, whereby a single control signal is effective to control the conductive state of the semiconductor device.

Claim 16

The semiconductor device of claim 1 wherein the semiconductor device comprises silicon.

Claim 17

The semiconductor device of claim 11 wherein said base region of said insulated-gate field-effect transistor comprises P conductivity type semiconductor material, and said drift and drain regions of said insulated-gate field-effect transistor comprise N conductivity type semiconductor material.

Claim 18

The semiconductor device in accordance with claim 1 further including a source region in successive arrangement with said base region, said channel region being contiguous with said source region and underlying said gate electrode.

Claim 19

The semiconductor device of claim 1 wherein said bias means controllably couples said carrier injection region to said drain region.

Claim 20

An insulated-gate semiconductor device with low on-resistance, comprising: (a) an insulated-gated field-effect transistor including, in successive arrangement, a drain region, a drift region, a base region and a channel region; said base region being of one conductivity type and said drain and drift regions being of the opposite conductivity type; and further including a plurality of external contacts for connection of said device into a circuit; a drain electrode attached to said drain region and ohmically connected to a first one of said external contacts, a source electrode attached to said base region and ohmically connected to a second one of said external contacts, and a gate electrode ohmically connected to a third one of said external contacts and insulatingly spaced from said channel region to determine the conductive state of said channel region in response to a bias voltage thereon; (b) a carrier injection region adjoining said drift region and being of the one conductivity type so as to form a P-N junction with said drift region, said carrier injection region being free of ohmic connections to said external contacts; and (c) means for controllably coupling said carrier injection region to said drain region comprising a first region of one type conductivity disposed within said drift region and a second region of said opposite type conductivity disposed within said first region.

Claim 21

An insulated-gate semiconductor device with low on-resistance, comprising: (a) an insulated-gated field-effect transistor including, in successive arrangement, a drain region, a drift region, a base region and a channel region; said base region being of one conductivity type and said drain and drift regions being of the opposite conductivity type; and further including a plurality of external contacts for connection of said device into a circuit; a drain electrode attached to said drain region and ohmically connected to a first one of said external contacts, a source electrode attached to said base region and ohmically connected to a second one of said external contacts, and a gate electrode ohmically connected to a third one of said external contacts and insulatingly spaced from said channel region to determine the conductive state of said channel region in response to a bias voltage thereon; (b) a carrier injection region adjoining said drift region and being of the one conductivity type so as to form a P-N junction with said drift region, said carrier injection region being free of ohmic connections to said external contacts; and (c) means for controllably coupling said carrier injection region to said drain region comprising a first region of one type conductivity disposed within said drift region and a second region of said opposite type conductivity disposed within said first region.

Claim 22

The semiconductor device of claim 16 wherein said means for coupling said carrier injection region to said drain region further comprises an insulated gate structure, associated with said first region, which in response to an appropriate applied bias, controllably couples opposite type conductivity carriers between said drift region and said second region.

Claim 23

The semiconductor device of claim 17 wherein said means for coupling said carrier injection region to said drain region includes an ohmic electrical connection between said first region and said carrier injection region.

Claim 24

The semiconductor device in accordance with claim 3 wherein said channel region is of said one conductivity type.

Claim 25

The semiconductor device in accordance with claim 6 wherein said channel region is of said one conductivity type.