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US4743885A
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Cyclic type D/A converter having error detection and correction system
Assignee: Fujitsu Ltd
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Filing: 1987-08-10
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Granted: 1988-05-10
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Expires: 2007-08-10
Abstract
Abstract A cyclic type D/A converter having an error detection and correction system including: a code conversion circuit for converting a binary code to a multi-states code; a digital-to-analog conversion circuit connected to the code conversion circuit for converting the multi-states code to an analog value; a detection circuit operatively connected to the digital-to-analog conversion circuit for converting the analog value to a digital code; and a control circuit operatively connected to the code conversion circuit, digital-to-analog conversion circuit and detection circuit for calculating a voltage difference between the analog value at a predetermined code value and another analog value adjacent to the predetermined code value, and for calculating a differential non-linearity error from the voltage difference based on the digital code, in order to obtain error and correction values of capacitors forming the digital-to-analog conversion circuit.
Inventors
- 👤 Osamu Kobayashi
- 👤 Yoshiaki Shimizu
- 👤 Kunihiko Gotoh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 22:05
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/66; H03M1/10; H03M1/1009; H03M1/1033; H03M1/1057; H03M1/1061; H03M1/667; H03M1/74; H03M1/80; H03M1/802; H03M1/804; H03M1/806
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
137 words
A cyclic type D/A converter having an error detection and correction system comprising: a code conversion means for converting a binary code to a multi-states code; a digital-to-analog conversion means operatively connected to said code conversion means for converting said multi-states code to an analog value; a detection means operatively connected to said digital-to-analog conversion means for converting said analog value to a digital code; and a control means operatively connected to said code conversion means, digital-to-analog conversion means and detection means, for calculating a voltage difference between said analog value at a predetermined code value and another analog value adjacent to said predetermined code value, and for calculating a differential non-linearity error from said voltage difference based on said digital code, in order to obtain error and correction values of capacitors forming said digital-to-analog conversion means.
Claim 2
Dependent Claim
137 words
A cyclic type D/A converter having an error detection and correction system comprising: a code conversion means for converting a binary code to a multi-states code; a digital-to-analog conversion means operatively connected to said code conversion means for converting said multi-states code to an analog value; a detection means operatively connected to said digital-to-analog conversion means for converting said analog value to a digital code; and a control means operatively connected to said code conversion means, digital-to-analog conversion means and detection means, for calculating a voltage difference between said analog value at a predetermined code value and another analog value adjacent to said predetermined code value, and for calculating a differential non-linearity error from said voltage difference based on said digital code, in order to obtain error and correction values of capacitors forming said digital-to-analog conversion means.
Claim 3
Dependent Claim
191 words
A cyclic type D/A converter as claimed in claim 1, wherein said digital-to-analog conversion means comprises: an operational amplifier having at least a non-inverting input terminal, an inverting input terminal and an output terminal; a first switching means provided between said inverting input terminal and said output terminal; a first capacitor connected to said inverting input terminal at one end thereof and connected to a second switching means for changing between an input terminal and an output terminal of said converter; a charging/discharging unit constituted by at least one capacitor and a third switching means, each of said capacitors being connected to said inverting input terminal at one end thereof and having approximately an equivalent capacitance value to that of said first capacitor, said third switching means being selectively connected to said output terminal or a reference voltage terminal or a ground terminal in correspondence with a sampling mode or a conversion mode; and correction means comprising a plurality of supplementary capacitors and switches, each of said supplementary capacitors and switches being connected in series, said correction means being connected in parallel to each of said capacitors forming said changing/discharging unit.
Claim 4
Dependent Claim
20 words
A cyclic type D/A converter as claimed in claim 1, wherein said multi-states code consists of a three states code.
Claim 5
Dependent Claim
17 words
A cyclic type D/A converter as claimed in claim 1, wherein said control means comprises a microcomputer.
Claim 6
Dependent Claim
20 words
A cyclic type D/A converter as claimed in claim 1, wherein said control means further comprises an error correction circuit.
Claim 7
Dependent Claim
62 words
A cyclic type D/A converter as claimed in claim 5, wherein said error correction circuit comprises a comparator for comparing a potential of said capacitors to be corrected with a reference voltage, an up-down counter for counting-up or down based on resultant data from said comparator, and a multiplication type D/A converter for dividing an analog voltage supplied to a supplementary capacitor.
Claim 8
Independent Claim
121 words
A method for detecting and correcting errors upon digital-to-analog conversion in a cyclic type D/A converter comprising steps of: converting a binary code to a multi-states code; converting said multi-states code to an analog value; detecting said analog value and again converting said analog value to a digital code; calculating a voltage difference between said analog value at a predetermined code value and another analog value at another code value adjacent to said predetermined code value based on said digital code; calculating a differential non-linearity error from said voltage difference using an approximation formula; obtaining a correction value based on said differential non-linearity error; and correcting a capacitance of a capacitor forming a digital-to-analog conversion unit based on said correction value.
Claim 9
Independent Claim
121 words
A method for detecting and correcting errors upon digital-to-analog conversion in a cyclic type D/A converter comprising steps of: converting a binary code to a multi-states code; converting said multi-states code to an analog value; detecting said analog value and again converting said analog value to a digital code; calculating a voltage difference between said analog value at a predetermined code value and another analog value at another code value adjacent to said predetermined code value based on said digital code; calculating a differential non-linearity error from said voltage difference using an approximation formula; obtaining a correction value based on said differential non-linearity error; and correcting a capacitance of a capacitor forming a digital-to-analog conversion unit based on said correction value.
Claim 10
Dependent Claim
64 words
A method for detecting and correcting errors as claimed in claim 7, wherein said predetermined code value is set to a position of 1/4 full scale and said another code value adjacent to said predetermined code value is set to a position of 1/4 full scale-1 least significant bit, where said digital-to-analog conversion unit comprises one calculation circuit for repeatedly calculating said analog value.
Claim 11
Dependent Claim
69 words
A method for detecting and correcting errors as claimed in claim 7, wherein said predetermined code value is set to the positions of 1/4 full scale and 1/8 full scale, and said another code value is set to the position of 1/4 full scale-1 least significant bit and 1/8 full scale-1 least significant bit, where said digital-to-analog conversion unit comprises two calculation circuits for repeatedly calculating said analog value.
Claim 12
Dependent Claim
22 words
A method for detecting and correcting errors as claimed in claim 7, wherein said multi-states code consists of a three states code.
References Cited (Backward Citations)
US4622536A
Cited
US4706066A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-05-10 | 1991-11-09 | 1992-05-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-05-10 | 1995-11-09 | 1996-05-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-05-10 | 1999-11-09 | 2000-05-10 | $7700.00 | Window Closed / Lapsed |