Patent US4743841A successfully refreshed from Google Patents.
US4743841A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor integrated circuit including circuit elements evaluating the same and having means for testing the circuit elements
Assignee: Fujitsu Ltd
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Filing: 1986-05-16
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Granted: 1988-05-10
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Expires: 2006-05-16
Abstract
Abstract A semiconductor integrated circuit including at lease one circuit (6, 8, 9, 71, 72, 104 to 106, 118, 119), at least one evaluating circuit element (10, 11, 12), a plurality of bonding pads (31 to 39) operatively connectable to the circuit and the evaluating circuit element, and a circuit for selectively connecting between the circuit and the bonding pads and between the evaluating circuit element and the bonding pads operatively connectable to the circuit. The selectively connecting circuit includes switching circuits (41 to 49) provided between the bonding pads and the evaluating circuit element and switching the connection between the bonding pads and the evaluating circuit element in response to a control signal. The semiconductor intergrated circuit may further include a circuit (Q 11 , Q 12 , 25, 58, 59) for controlling the at least one circuit to have a high impedance as seen from the bonding pads, in response to the control signal. The selectively connecting circuit may further include a circuit (2, 2') for outputting the control signal in response to reception of a test request signal.
Inventors
- 👤 Atsushi Takeuchi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 07:52
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/2851; G01R31/2884
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
190 words
A semiconductor integrated circuit comprising: at least one integrated circuit; at least one evaluating circuit element for evaluating said integrated circuit; and a testing means for testing said at least one integrated circuit by testing said at least one evaluating circuit element, said testing means including a plurality of bonding pads connected to said at least one integrated circuit and said at least one evaluating circuit element, selective means for selectively connecting between said at least one integrated circuit and said plurality of bonding pads during normal operation of said at least one integrated circuit, and said selective means for selectively connecting between at least one evaluating circuit element and said bonding pads connecting to said at least one integrated circuit during testing of said at least one evaluating circuit element, and switching means provided between said plurality of bonding pads and said at least one evaluating circuit element, said switching means for switching the connection between said plurality of bonding pads and said at least one evaluating circuit element in response to a control signal to enable said testing means to test said at least one evaluating circuit element.
Claim 2
Dependent Claim
190 words
A semiconductor integrated circuit comprising: at least one integrated circuit; at least one evaluating circuit element for evaluating said integrated circuit; and a testing means for testing said at least one integrated circuit by testing said at least one evaluating circuit element, said testing means including a plurality of bonding pads connected to said at least one integrated circuit and said at least one evaluating circuit element, selective means for selectively connecting between said at least one integrated circuit and said plurality of bonding pads during normal operation of said at least one integrated circuit, and said selective means for selectively connecting between at least one evaluating circuit element and said bonding pads connecting to said at least one integrated circuit during testing of said at least one evaluating circuit element, and switching means provided between said plurality of bonding pads and said at least one evaluating circuit element, said switching means for switching the connection between said plurality of bonding pads and said at least one evaluating circuit element in response to a control signal to enable said testing means to test said at least one evaluating circuit element.
Claim 3
Dependent Claim
39 words
A semiconductor integrated circuit according to claim 1 further comprising a high-impedance making means for controlling said at least one integrated circuit to have a high impedance as seen from said bonding pads in response to said control signal.
Claim 4
Dependent Claim
41 words
A semiconductor integrated circuit according to claim 2, wherein said integrated circuit comprises an output driver connected to said bonding pad, and wherein said high-impedance making means comprises a switching element deenergizing said output driver in response to said control signal.
Claim 5
Dependent Claim
58 words
A semiconductor integrated circuit according to claim 2, wherein said circuit comprises an input driver connected to said bonding pad and having a low impedance to said bonding pad, and wherein said high-impedance making means comprises a circuit (25, 58) electrically disconnecting a line from said input driver to said bonding pad in response to said control signal.
Claim 6
Dependent Claim
32 words
A semiconductor integrated circuit according to claim 1, wherein said selective means further comprises control signal outputting means for outputting said control signal in response to reception of a test request signal.
Claim 7
Dependent Claim
32 words
A semiconductor integrated circuit according to claim 5, wherein said control signal outputting means is connected to a bonding pad of said plurality of bonding pads to receive said test request signal.
Claim 8
Dependent Claim
92 words
A semiconductor integrated circuit according to claim 6, wherein said bonding pad connected to said control signal outputting means is connected to said circuit integrated, and integrated wherein said control signal outputting means comprises a transistor having a thresold voltage higher than a normal voltage supplied to said bonding pad for operating said circuit, said control signal outputting means being not operable to the application of said normal voltage to said bonding pad and being operable to the application of said test request signal having a voltage higher than said threshold voltage.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-05-10 | 1991-11-09 | 1992-05-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-05-10 | 1995-11-09 | 1996-05-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-05-10 | 1999-11-09 | 2000-05-10 | $7700.00 | Window Closed / Lapsed |