Diagnosing method for logic circuits

Claim 2

In a method for testing a logic circuit which comprises a plurality of partial circuits each including a logic block having an input side and an output side, an input side data holding stage including a plurality of circuit elements for holding information data received and being operatively connected to said logic block input side for transmitting the information thereto, an output side data holding stage including at least one circuit element operatively connected to said logic block output side for receiving and holding information data therefrom and a scan circuit segment associated with and operatively connected in each partial circuit for inputting and outputting diagnostic data, the improvement comprising the steps of: within each partial circuit, actuating the scan circuit segment and inhibiting operation of the logic block; scanning-in predetermined diagnostic input data directly into said output side data holding stage by said scan circuit segment while maintaining any information data that may be present at the input side data holding stage circuit elements and its condition thereof as indeterminate; reading out the content of the output side data holding stage via said scan circuit segment as diagnostic data for said scan circuit segment; and repeating the above said steps until all of said partial circuits have been diagnosed.

Claim 5

In a method for testing a logic circuit which comprises a plurality of partial circuits each including a logic block having an input side and an output side, an input side data holding stage for holding information data received and being operatively connectd to said logic block input side for transmitting the information thereto, an output side data holding stage operatively connected to said logic block output side for receiving and holding the information data therefrom and a scan circuit segment associated with and operatively connected in each partial circuit for inputting and outputting diagnostic data, including in each of said partial circuits the steps of actuating the scan circuit segment and setting predetermined diagnostic data in said input side data holding stage, inhibiting the operation of said scan circuit segment and activating said logic block so that it becomes responsive to the diagnostic data content in said input data holding stage, placing the logic block operational result in the output side data holding stage and scanning-out the content in said output side data holding stage as diagnostic data for the logic block and holding stages, wherein the improvement comprises the further steps of: within each partial circuit actuating said scan circuit segment and inhibiting operation of said logic block; scanning-in diagnostic input data directly into said output side data holding stage by said scan circuit segment while maintaining any information data that may be present at the input data holding stage and its condition thereof as indeterminate; and reading out the content of the output side data holding stage via said scan circuit segment as diagnostic data for said scan circuit segment.

Claim 6

In a method for testing a logic circuit which comprises a plurality of partial circuits each including a logic block having an input side and an output side, an input side data holding stage for holding information data received and being operatively connectd to said logic block input side for transmitting the information thereto, an output side data holding stage operatively connected to said logic block output side for receiving and holding the information data therefrom and a scan circuit segment associated with and operatively connected in each partial circuit for inputting and outputting diagnostic data, including in each of said partial circuits the steps of actuating the scan circuit segment and setting predetermined diagnostic data in said input side data holding stage, inhibiting the operation of said scan circuit segment and activating said logic block so that it becomes responsive to the diagnostic data content in said input data holding stage, placing the logic block operational result in the output side data holding stage and scanning-out the content in said output side data holding stage as diagnostic data for the logic block and holding stages, wherein the improvement comprises the further steps of: within each partial circuit actuating said scan circuit segment and inhibiting operation of said logic block; scanning-in diagnostic input data directly into said output side data holding stage by said scan circuit segment while maintaining any information data that may be present at the input data holding stage and its condition thereof as indeterminate; and reading out the content of the output side data holding stage via said scan circuit segment as diagnostic data for said scan circuit segment.

Claim 7

A method for testing a logic circuit according to claim 3, wherein the entire logic circuit section, corresponding to the logic blocks and the respective input side and output side data holding stages in said plurality of partial circuits, is diagnosed first followed by diagnosing the entire scan circuit section, corresponding to the scan circuit segments in said plurality of partial circuits.

Claim 8

A method for testing a logic circuit according to claim 3, wherein the entire scan circuit section, corresponding to the scan circuit segments in said plurality of partial circuits is diagnosed first followed by diagnosing the entire logic circuit section, corresponding to the logic blocks and the respective input side and output side data holding stages in said plurality of partial circuits.

Claim 9

A method for testing a logic circuit according to claim 3, wherein each partial circuit is individually tested by testing the respective logic circuit segment, including the logic block in conjunction with the input side and output side data holding stages as well as the scan circuit segment therein until said entire plurality of partial circuits are tested.

Claim 10

A method for testing a logic circuit according to claim 1, wherein the input side data holding stage in respective partial circuits is used as the output side data holding stage of an adjacent partial circuit and the output side data holding stage in each of said respective partial circuit is used as the input side data holding stage of a different adjacent partial circuit.

Claim 11

A method for testing a logic circuit according to claim 2, wherein the input side data holding stage in respective partial circuits is used as the output side data holding stage of an adjacent partial circuit and the output side data holding stage in each of said respective partial circuits is used as the input side data holding stage of a different adjacent partial circuit.

Claim 12

A method for testing a logic circuit according to claim 3, wherein the input side data holding stage in respective partial circuits is used as the output side data holding stage of an adjacent partial circuit and the output side data holding stage in each of said respective partial circuits is used as the input side data holding stage of a different adjacent partial circuit.