Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
161 words
A semiconductor integrated circuit comprising: an internal circuit; means for receiving an externally generated chip select signal; means for receiving an externally generated input signal; and a voltage detecting circuit for detecting whether or not the potential of said input signal is higher than a predetermined reference potential, said voltage detecting circuit comprising: a first means for differentially comparing the potential of said input signal with said predetermined reference potential and generating a predetermined output potential in accordance with the results of the comparison, a second means for detecting a predetermined edge of said chip select signal so as to trigger said first means, and a third means for latching said output potential of said first means to said third means when said first means is triggered by said second means; said internal circuit being switched from a first mode of operation to a second mode of operation, or vice versa, in accordance with the output potential of said third means.
Claim 2
Dependent Claim
161 words
A semiconductor integrated circuit comprising: an internal circuit; means for receiving an externally generated chip select signal; means for receiving an externally generated input signal; and a voltage detecting circuit for detecting whether or not the potential of said input signal is higher than a predetermined reference potential, said voltage detecting circuit comprising: a first means for differentially comparing the potential of said input signal with said predetermined reference potential and generating a predetermined output potential in accordance with the results of the comparison, a second means for detecting a predetermined edge of said chip select signal so as to trigger said first means, and a third means for latching said output potential of said first means to said third means when said first means is triggered by said second means; said internal circuit being switched from a first mode of operation to a second mode of operation, or vice versa, in accordance with the output potential of said third means.
Claim 3
Dependent Claim
23 words
A semiconductor integrated circuit according to claim 1, wherein said first mode of operation is a normal mode for operating said internal circuit.
Claim 4
Dependent Claim
23 words
A semiconductor integrated circuit according to claim 1, wherein said second mode of operation is a test mode for testing said internal circuit.
Claim 5
Dependent Claim
26 words
A semiconductor integrated circuit according to claim 1, wherein the potential of said input signal is higher than said predetermined reference potential in a test mode.
Claim 6
Dependent Claim
28 words
A semiconductor integrated circuit according to claim 1, wherein the potential of said input signal is lower than said predetermined reference potential in a normal mode of operation.
Claim 7
Dependent Claim
26 words
A semiconductor integrated circuit according to claim 1, wherein said predetermined reference potential is obtained from a power source line connected to said voltage detecting circuit.
Claim 8
Dependent Claim
23 words
A semiconductor integrated circuit according to claim 1, wherein said externally generated chip select signal is also used as a row enable signal.
Claim 9
Dependent Claim
62 words
A semiconductor integrated circuit according to claim 1, further comprising a predetermined number of address terminals for said internal circuit, wherein said internal circuit comprises a decoder for selecting one of a plurality of memory blocks in said internal circuit in a normal mode of operation and said externally generated input signal is supplied to an address terminal connected to said decoder.
Claim 10
Dependent Claim
55 words
A semiconductor integrated circuit according to claim 1, further comprising a data input terminal and a data output terminal for said internal circuit, wherein said externally generated input signal is supplied to one of said data input terminal and data output terminal in synchronism with the predetermined edge of said externally generated chip select signal.