Analog-to-digital converter

Claim 2

An analog-to-digital converter, not requiring a clock drive, for converting an analog signal to an N-bit digital signal, the converter comprising: an N-tap acoustic charge transport delay line for receiving and containing an injected analog signal, with the N taps being spaced apart from one another along the delay line at predetermined intervals and with each tap non-invasively sensing and forming a replica of the amplitude of the analog signal currently passing that tap, and with the delay line including a channel region for propagating the analog signal; wave means coupled to the delay line, for generating a surface acoustic wave and introducing this wave into the delay line, wherein the surface acoustic wave collects an injected analog signal into charge packets and transports the charge packets through the channel region of the delay line; N reference signal means for supplying N voltage reference signals; N comparators, each having at least two input terminals and one output terminal, with one input terminal of comparator i (i=1,2, . . . ,N) coupled to the i-th tap of the delay line and a second input terminal of comparator i coupled to the output signal of the i-th reference signal means, for comparing the signals received at these two input terminals and for generating an output signal of comparator i that is an i-th bit of the desired N-bit digital signal; a shift register array having storage for at least N bits, with the storage for bit i being coupled to the output terminal of comparator i (i=1,2, . . . ,N); wherein the reference signal for the first comparator is substantially constant and the m-th reference signal (m=2,3, . . . ,N) is determined from the values of bits 1, . . . ,m-1 and from the first comparator reference signal.

Claim 3

The A/D converter of claim 1, wherein said reference signal means m=2,3,. . . ,N comprise N-1 parallel bit digital-to-analog converters and said reference signal means m is coupled between said shift register array and said comparator m.

Claim 4

The A/D converter of claim 1, wherein said channel region of said delay line is formed of GaAs.

Claim 5

The A/D converter of claim 1, wherein said N taps lie at substantially equal linear intervals along said delay line.

Claim 6

The A/D converter of claim 4, wherein said surface acoustic wave transports said charge packets from said one tap to said next tap in substantially equal time intervals.

Claim 7

An analog-to-digital converter, not requiring a clock drive, for converting an analog signal to an N-bit digital signal, the converter comprising: an N-tap acoustic charge transport line for receiving and containing an injected analog signal, with the delay line including k parallel channel regions for propagating the analog signal, where k is a predetermined integer 1, with the taps on each parallel channel region being spaced apart from one another at predetermined intervals and with each tap noninvasively sensing and forming a replica of the amplitude of the analog signal currently passing that tap; wave means coupled to the delay line, for generating a surface acoustic wave and introducing this wave into the delay line, wherein the surface acoustic wave collects an injected analog signal into charge packets and transports the charge packets through one of the channel regions of the delay line; N reference signal means for supplying N voltage reference signals; N comparators, each having at least two input terminals and one output terminal, with one input terminal of comparator i (i=1,2,. . . ,N) coupled to the i-th tap of the delay line and a second input terminal of comparator i coupled to the output signal of the i-th reference signal means, for comparing the signals received at these two input terminals and for generating an output signal of comparator i that is an i-th bit of the desired N-bit digital signal; a shift register array having storage for at least N bits, with the storage for bit i being coupled to the output terminal of comparator i (i=1,2,. . . ,N); wherein the reference signal for the first comparator is substantially constant and the m-th reference signal (m=2,3,. . ., N) is determined from the values of bits 1,. . ., m-1 and from the first comparator reference signal.

Claim 8

An analog-to-digital converter, not requiring a clock drive, for converting an analog signal to an N-bit digital signal, the converter comprising: an N-tap acoustic charge transport line for receiving and containing an injected analog signal, with the delay line including k parallel channel regions for propagating the analog signal, where k is a predetermined integer 1, with the taps on each parallel channel region being spaced apart from one another at predetermined intervals and with each tap noninvasively sensing and forming a replica of the amplitude of the analog signal currently passing that tap; wave means coupled to the delay line, for generating a surface acoustic wave and introducing this wave into the delay line, wherein the surface acoustic wave collects an injected analog signal into charge packets and transports the charge packets through one of the channel regions of the delay line; N reference signal means for supplying N voltage reference signals; N comparators, each having at least two input terminals and one output terminal, with one input terminal of comparator i (i=1,2,. . . ,N) coupled to the i-th tap of the delay line and a second input terminal of comparator i coupled to the output signal of the i-th reference signal means, for comparing the signals received at these two input terminals and for generating an output signal of comparator i that is an i-th bit of the desired N-bit digital signal; a shift register array having storage for at least N bits, with the storage for bit i being coupled to the output terminal of comparator i (i=1,2,. . . ,N); wherein the reference signal for the first comparator is substantially constant and the m-th reference signal (m=2,3,. . ., N) is determined from the values of bits 1,. . ., m-1 and from the first comparator reference signal.

Claim 9

The A/D converter of claim 6, wherein said taps in each of said parallel channel regions lie at substantially equal linear intervals along said channel region.

Claim 10

The A/D converter of claim 7, wherein said reference signal means m=2, . . . ,N comprise N-1 parallel bit digital-to-analog converters and said reference signal means m is coupled between said shift register array and said comparator m.

Claim 11

The A/D converter of claim 8, wherein each of said parallel channel regions of said delay line is formed of gallium arsenide.

Claim 12

The A/D converter of claim 7, wherein said surface acoustic wave transports said charge packets from said one tap to said next tap in substantially equal time intervals.