N-bit propagatary analog-to-digital converter system

Claim 1

An improved n-bit propagatory analog-to-digital converter system having n stages for converting an analog data into a parallel binary output number, which comprises: a plurality of analog shift registers ASR 1 -ASR n-1 , arranged in a predetermined manner so as to comprise an analog delay line, and wherein each of said plurality of analog shift registers includes a peristaltic charge-coupled-device; a plurality of digital shift registers DSR 1 -DSR n-1 , arranged in a predetermined manner so as to comprise a digital delay line, and wherein each of said plurality of digital shift registers includes a flip-flop for the first stage of said improved n-bit propagatory analog-to-digital converter, two flip-flops for the second stage, three flip-flops for the third stage up to n-1 stages; a plurality of threshold detectors TD 1 -TD n , each operatively connected at one of its inputs to said analog delay line in each of the stages 1 through n; a plurality of digital-to-analog converters DAC 1 -DAC n-1 , operatively connected to the other inputs of corresponding ones of said threshold detectors, to said digital shift registers and to each other, DAC 1 being a 1-bit current source DAC and connected in stage 2, DAC 2 being a 2-bit current source DAC and connected in stage 3, DAC 3 being a 3-bit current DAC source and connected in stage 4, . . . up to the n th stage; and a multiple phase clock having a series of outputs operatively connected to said analog delay line and another output operatively connected to said digital delay line such that they operate in synchronization, and such that each stage from (1) to n of said n-bit propagatory analog-to-digital converter adds one more bit to the conversion as the analog data, inputted at the input of analog shift register ASR 1 , propagates down said analog delay line, and is compared to a reference signal for each of the stages.