RF switch with diode network and control latch sharing common element

Claim 2

An RF switch, comprising: a diode network having a series branch coupled between first and second signal ports and having a shunt branch coupled between a circuit node in said series branch and a source of reference potential; a latching circuit comprising a pair of transistors having respective control electrodes and conduction paths cross-coupled to provide positive feedback therebetween such that each transistor of said pair controls the conductive state of the other, said latching circuit having a first state in which one transistor of said pair is conductive and a second state in which said one transistor is non-conductive; circuit means coupling said conduction path of said one transistor in parallel with said shunt branch of said diode network; and bias means, including a first impedence means coupled between an output electrode of a selected one of said transistors and a point in said series branch and a second impedance means coupled between said output electrode of said selected transistor and a point in said shunt branch, said bias means being responsive to said first state of said latching circuit, for applying forward bias to said shunt branch and reverse bias to said series branch of said diode network and responsive to said second state of said latching circuit for reversing said bias applied to said branches.

Claim 3

An RF switch as recited in claim 1 wherein said transistors are of complementary type tending to bias each other on in response to said feedback and further comprising control means coupled to said control electrode of the other one of said pair of transistors and responsive to a control signal supplied thereto for interrupting said feedback for turning said complementary transistors off.

Claim 4

An RF switch, comprising: a diode network having a series branch coupled between first and second signal ports and a shunt branch coupled between a circuit node in said series branch and a source of reference potential; a latching circuit comprising a pair of complementary transistors having respective conduction paths and control electrodes cross-coupled so as to bias both said transistors on, said conduction path of one of said complementary transistors being connected in parallel with said shunt branch of said diode network; a control means coupled to said latching circuit for inhibiting turn-on of said pair of transistors in response to a control signal; bias means responsive to turn-on of said complementary transistors for applying forward bias to said shunt branch and reverse bias to said series branch and responsive to turn-off of said complementary transistors for applying forward bias to said series branch and reverse bias to said shunt branch, and wherein said bias means comprises a first impedance means coupled between an output electrode of a selected one of said transistors and a point in said series branch and a second impedance means coupled between said output electrode of said selected transistor and a point in said shunt branch.

Claim 5

An RF switch, comprising: a diode network having a series branch coupled between first and second signal ports and a shunt branch coupled between a circuit node in said series branch and a source of reference potential; a latching circuit comprising a pair of complementary transistors having respective conduction paths and control electrodes cross-coupled so as to bias both said transistors on, said conduction path of one of said complementary transistors being connected in parallel with said shunt branch of said diode network; a control means coupled to said latching circuit for inhibiting turn-on of said pair of transistors in response to a control signal; bias means responsive to turn-on of said complementary transistors for applying forward bias to said shunt branch and reverse bias to said series branch and responsive to turn-off of said complementary transistors for applying forward bias to said series branch and reverse bias to said shunt branch, and wherein said bias means comprises a first impedance means coupled between an output electrode of a selected one of said transistors and a point in said series branch and a second impedance means coupled between said output electrode of said selected transistor and a point in said shunt branch.

Claim 6

An RF switching circuit, comprising: a T-network comprising first and second diodes coupled between a circuit node and respective ones of first and second signal ports, said circuit node being coupled to a source of reference potential via a third diode; a latching circuit comprising first and second complementary transistors, said first transistor having a conduction path coupled in parallel with said third diode and having a control electrode coupled via the conduction path of said second transistor to a second source of reference potential, said second transistor having a control electrode coupled to said circuit node, said latching circuit having a first state in which said conduction paths are concurrently conductive and a second state in which said conduction paths are concurrently non-conductive; control means coupled to said control electrode of said second transistor and responsive to a control signal supplied thereto for controlling said states of said latching circuit; and bias means comprising resistor means coupled between an output electrode of said second transistor and each one of said first, second, and third diodes of said T-network responsive to said first state of said latching circuit for applying forward bias to said third diode and reverse bias to said first and second diodes and responsive to said second state of said latching circuit for applying reverse bias to said third diode and forward bias to said first and second diodes.

Claim 7

An RF switching circuit, comprising: a T-network comprising first and second diodes coupled between a circuit node and respective ones of first and second signal ports, said circuit node being coupled to a source of reference potential via a third diode; a latching circuit comprising first and second complementary transistors, said first transistor having a conduction path coupled in parallel with said third diode and having a control electrode coupled via the conduction path of said second transistor to a second source of reference potential, said second transistor having a control electrode coupled to said circuit node, said latching circuit having a first state in which said conduction paths are concurrently conductive and a second state in which said conduction paths are concurrently non-conductive; control means coupled to said control electrode of said second transistor and responsive to a control signal supplied thereto for controlling said states of said latching circuit; and bias means comprising resistor means coupled between an output electrode of said second transistor and each one of said first, second, and third diodes of said T-network responsive to said first state of said latching circuit for applying forward bias to said third diode and reverse bias to said first and second diodes and responsive to said second state of said latching circuit for applying reverse bias to said third diode and forward bias to said first and second diodes.

Claim 8

An RF switching circuit, comprising: a T-network comprising first and second diodes coupled between a circuit node and respective ones of first and second signal ports, said circuit node being coupled to a source of reference potential via a third diode; a latching circuit comprising first and second complementary transistors, said first transistor having a conduction path coupled in parallel with said third diode and having a control electrode coupled via the conduction path of said second transistor to a second source of reference potential, said second transistor having a control electrode coupled to said circuit node, said latching circuit having a first state in which said conduction paths are concurrently conductive and a second state in which said conduction paths are concurrently non-conductive; control means coupled to said control electrode of said second transistor and being responsive to a control signal supplied thereto for controlling said states of said latching circuit; bias means connected to an output electrode of said second transistor and being responsive to said first state of said latching circuit for applying forward bias to said third diode and reverse bias to said first and second diodes and responsive to said second state of said latching circuit for applying reverse bias to said third diode and forward bias to said first and second diodes, and wherein: said first transistor is of NPN type, said second transistor is of PNP type and said control means comprises a third transistor of PNP type having emitter and collector electrodes connected to respective emitter and base electrodes of said second transistor and having a base electrode coupled to receive said control signal.

Claim 9

An RF switching circuit, comprising: a T-network comprising first and second diodes coupled between a circuit node and respective ones of first and second signal ports, said circuit node being coupled to a source of reference potential via a third diode; a latching circuit comprising first and second complementary transistors, said first transistor having a conduction path coupled in parallel with said third diode and having a control electrode coupled via the conduction path of said second transistor to a second source of reference potential, said second transistor having a control electrode coupled to said circuit node, said latching circuit having a first state in which said conduction paths are concurrently conductive and a second state in which said conduction paths are concurrently non-conductive; control means coupled to said control electrode of said second transistor and being responsive to a control signal supplied thereto for controlling said states of said latching circuit; bias means connected to an output electrode of said second transistor and being responsive to said first state of said latching circuit for applying forward bias to said third diode and reverse bias to said first and second diodes and responsive to said second state of said latching circuit for applying reverse bias to said third diode and forward bias to said first and second diodes, and wherein: said first transistor is of NPN type, said second transistor is of PNP type and said control means comprises a third transistor of PNP type having emitter and collector electrodes connected to respective emitter and base electrodes of said second transistor and having a base electrode coupled to receive said control signal.

Claim 10

An RF switching circuit, comprising: a T-network comprising first and second diodes coupled between a circuit node and respective ones of first and second signal ports, said circuit node being coupled to a source of reference potential via a third diode; a latching circuit comprising first and second complementary transistors, said first transistor having a conduction path coupled in parallel with said third diode and having a control electrode coupled via the conduction path of said second transistor to a second source of reference potential, said second transistor having a control electrode coupled to said circuit node, said latching circuit having a first state in which said conduction paths are concurrently conductive and a second state in which said conduction paths are concurrently non-conductive; control means coupled to said control electrode of said second transistor and being responsive to a control signal supplied thereto for controlling said states of said latching circuit; bias means connected to an output electrode of said second transistor and being responsive to said first state of said latching circuit for applying forward bias to said third diode and reverse bias to said first and second diodes and responsive to said second state of said latching circuit for applying reverse bias to said third diode and forward bias to said first and second diodes, and wherein: said control means comprises a third transistor having a conduction path connected between a selected one of said sources of reference potential and said control electrode of a selected one of said first and second transistors and having a control electrode connected to receive said control signal.

Claim 11

An RF switching circuit, comprising: a T-network comprising first and second diodes coupled between a circuit node and respective ones of first and second signal ports, said circuit node being coupled to a source of reference potential via a third diode; a latching circuit comprising first and second complementary transistors, said first transistor having a conduction path coupled in parallel with said third diode and having a control electrode coupled via the conduction path of said second transistor to a second source of reference potential, said second transistor having a control electrode coupled to said circuit node, said latching circuit having a first state in which said conduction paths are concurrently conductive and a second state in which said conduction paths are concurrently non-conductive; control means coupled to said control electrode of said second transistor and being responsive to a control signal supplied thereto for controlling said states of said latching circuit; bias means connected to an output electrode of said second transistor and being responsive to said first state of said latching circuit for applying forward bias to said third diode and reverse bias to said first and second diodes and responsive to said second state of said latching circuit for applying reverse bias to said third diode and forward bias to said first and second diodes, and wherein: said control means comprises a third transistor having a conduction path connected between a selected one of said sources of reference potential and said control electrode of a selected one of said first and second transistors and having a control electrode connected to receive said control signal.

Claim 12

An RF switching circuit, comprising: a T-network comprising first and second diodes coupled between a circuit node and respective ones of first and second signal ports, said circuit node being coupled to a source of reference potential via a third diode; a latching circuit comprising first and second complementary transistors, said first transistor having a conduction path coupled in parallel with said third diode and having a control electrode coupled via the conduction path of said second transistor to a second source of reference potential, said second transistor having a control electrode coupled to said circuit node, said latching circuit having a first state in which said conduction paths are concurrently conductive and a second state in which said conduction paths are concurrently non-conductive; controls means coupled to said control electrode of said second transistor and being responsive to a control signal supplied thereto for controlling said states of said latching circuit; bias means connected to an output electrode of said second transistor and being responsive to said first state of said latching circuit for applying forward bias to said third diode and reverse bias to said first and second diodes and responsive to said second state of said latching circuit for applying reverse bias to said third diode and forward bias to said first and second diodes, and wherein: said control means includes a bias signal source for applying turn-on bias to at least one of said control electrodes of said first and second transistors for initiating said first state of said latching circuit and a further transistor having a conduction path connected between one of said control electrodes and one of said sources of reference potential and having a control electrode coupled to receive said control signal, said further transistor being responsive to said control signal for placing said latching circuit in said second state when said control signal is present.

Claim 13

An RF switching circuit, comprising: a T-network comprising first and second diodes coupled between a circuit node and respective ones of first and second signal ports, said circuit node being coupled to a source of reference potential via a third diode; a latching circuit comprising first and second complementary transistors, said first transistor having a conduction path coupled in parallel with said third diode and having a control electrode coupled via the conduction path of said second transistor to a second source of reference potential, said second transistor having a control electrode coupled to said circuit node, said latching circuit having a first state in which said conduction paths are concurrently conductive and a second state in which said conduction paths are concurrently non-conductive; controls means coupled to said control electrode of said second transistor and being responsive to a control signal supplied thereto for controlling said states of said latching circuit; bias means connected to an output electrode of said second transistor and being responsive to said first state of said latching circuit for applying forward bias to said third diode and reverse bias to said first and second diodes and responsive to said second state of said latching circuit for applying reverse bias to said third diode and forward bias to said first and second diodes, and wherein: said control means includes a bias signal source for applying turn-on bias to at least one of said control electrodes of said first and second transistors for initiating said first state of said latching circuit and a further transistor having a conduction path connected between one of said control electrodes and one of said sources of reference potential and having a control electrode coupled to receive said control signal, said further transistor being responsive to said control signal for placing said latching circuit in said second state when said control signal is present.