Counter circuit having flip-flops for synchronizing carry signals between stages

Claim 2

A multistage circuit comprising a plurality of counting stages connected in cascade, each providing a carry signal and having signal logic levels at an output of each counting stage inverted by main clock pulses and sub clock pulses; and means including a flip-flop connected at the output of each counting stage except the first stage to receive the carry signal from that counting stage and the carry signal from a preceding counting stage and supplied with said main clock pulses for synchronizing the carry signals of that counting stage and the preceding counting stage with the main clock pulses to generate a carry signal to said flip-flop means of a succeeding counting stage unaffected by delays in the carry signal of the preceding counting stage.

Claim 3

A multistage counter circuit employing main clock pulses having a predetermined pulse period and sub clock pulses having a pulse period equal to that of the main clock pulses and a predetermined phase difference relative to phases of the main clock pulses comprising a plurality of counting stages connected in cascade, each provided with transfer gates operable in response to the main and sub clock pulses and signal lines connected between said transfer gates to obtain logic levels of said counting stages at a plurality of predetermined points, the signal logic levels at first points in said counting stages being inverted signal logic levels at second points by the operation of the transfer gates in response to the sub clock pulses, the inverted signal logic levels being applied directly to a third point in a first counting stage whereas in subsequent counting stages the inverted signal logic levels at second points are transferred to third points in response to the operation of the transfer gates connected therebetween, the signal logic levels at the third points being applied to the first points by the operation of the transfer gates in response to the main clock pulses, each of said counting stages further providing a carry signal indicative of a carry state of corresponding counting stages; means including a flip-flop and an AND gate connected at the first point of each of said subsequent counting stages for synchronizing the carry signal of each stage with the main clock pulses to generate a carry signal to a succeeding stage unaffected by delays in the carry signal of a preceding stage.

Claim 4

A multistage counter circuit employing main clock pulses having a predetermined pulse period and sub clock pulses having a pulse period equal to that of the main clock pulses and a predetermined phase difference relative to phases of the main clock pulses comprising a plurality of counting stages connected in cascade, each provided with transfer gates operable in response to the main and sub clock pulses and signal lines connected between said transfer gates to obtain logic levels of said counting stages at a plurality of predetermined points, the signal logic levels at first points in said counting stages being inverted signal logic levels at second points by the operation of the transfer gates in response to the sub clock pulses, the inverted signal logic levels being applied directly to a third point in a first counting stage whereas in subsequent counting stages the inverted signal logic levels at second points are transferred to third points in response to the operation of the transfer gates connected therebetween, the signal logic levels at the third points being applied to the first points by the operation of the transfer gates in response to the main clock pulses, each of said counting stages further providing a carry signal indicative of a carry state of corresponding counting stages; means including a flip-flop and an AND gate connected at the first point of each of said subsequent counting stages for synchronizing the carry signal of each stage with the main clock pulses to generate a carry signal to a succeeding stage unaffected by delays in the carry signal of a preceding stage.

Claim 5

A multistage counter circuit comprising means providing main clock pulses and sub clock pulses, a plurality of counting stages connected in cascade, each providing a carry signal and having signal logic levels at an output of each counting stage inverted by the main clock pulses and sub clock pulses, and means including a flip-flop connected at the output of each counting stage except the first stage to receive the carry signal from that counting stage and the carry signal from a preceding counting stage and supplied with said main clock pulses for synchronizing the carry signals of that counting stage and the preceding counting stage with the main clock pulses to generate a carry signal to said flip-flop means a succeeding counting stage unaffected by delay in the carry signal of the preceding counting stage.

Claim 6

A multistage counter circuit comprising means providing main clock pulses and sub clock pulses, a plurality of counting stages connected in cascade, each providing a carry signal and having signal logic levels at an output of each counting stage inverted by the main clock pulses and sub clock pulses, and means including a flip-flop connected at the output of each counting stage except the first stage to receive the carry signal from that counting stage and the carry signal from a preceding counting stage and supplied with said main clock pulses for synchronizing the carry signals of that counting stage and the preceding counting stage with the main clock pulses to generate a carry signal to said flip-flop means a succeeding counting stage unaffected by delay in the carry signal of the preceding counting stage.