US4741002A
Expired / Lapsed
US
⏱️ 0.0 years remaining
RMS calculation circuit
Assignee: General Electric Co
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Filing: 1987-01-29
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Granted: 1988-04-26
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Expires: 2007-01-29
Abstract
Abstract The root mean square value of sensed current within a protected circuit is calculated. A frequency multiplying circuit produces a pulse stream having a frequency proportional to the square of the amplitude of an analog signal representation of the circuit current. A root mean square value over a prescribed interval is developed from the squared current value.
Inventors
- 👤 John J. Dougherty
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 00:32
CPC Classifications
G; G01; G01R; G01R19/00; G01R19/165; G01R19/16528; G01R19/02; H; H02; H02H; H02H3/00; H02H3/08; H02H3/093; H02H3/0935
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
170 words
An RMS determining circuit comprising: a divide-by-N counter having one input connected with a frequency multiplier for receiving a first frequency proportional to a multiple of current flowing through a power circuit and having another input connected with a sample frequency source for receiving a predetermined second frequency and generating an output frequency less than said first frequency; an UP-counter having a first input connected with said divide-by-N counter for receiving said output frequency and having a clear input for receiving said predetermined second frequency, said UP-counter providing an m-bit representation of said first frequency at an output; and an m+1 bit latch having one input connected with said sample frequency source and another input connected within an m-bit adder, an output on said m+1 bit latch being connected with said divide-by-N counter a first input on said m-bit adder and a CARRY-IN input on said m-bit ADDER for providing an RMS representation of said circuit current, a second input to said m-bit ADDER being connected with said UP counter.
Claim 2
Dependent Claim
170 words
An RMS determining circuit comprising: a divide-by-N counter having one input connected with a frequency multiplier for receiving a first frequency proportional to a multiple of current flowing through a power circuit and having another input connected with a sample frequency source for receiving a predetermined second frequency and generating an output frequency less than said first frequency; an UP-counter having a first input connected with said divide-by-N counter for receiving said output frequency and having a clear input for receiving said predetermined second frequency, said UP-counter providing an m-bit representation of said first frequency at an output; and an m+1 bit latch having one input connected with said sample frequency source and another input connected within an m-bit adder, an output on said m+1 bit latch being connected with said divide-by-N counter a first input on said m-bit adder and a CARRY-IN input on said m-bit ADDER for providing an RMS representation of said circuit current, a second input to said m-bit ADDER being connected with said UP counter.
Claim 3
Dependent Claim
32 words
The RMS determining circuit of claim 1 wherein said output frequency equals said first frequency divided by the m-bit binary value from the most significant bits of from said m+1 bit latch.
Claim 4
Dependent Claim
54 words
The RMS determining circuit of claim 1 wherein said m+1 bit latch provides an "m" data bit to said divide-by-N counter, said m data bit being representative of a most significant data bit, and a "1" data bit to said m-bit ADDER said "1" data bit being representative of a least significant data bit.
Claim 5
Dependent Claim
21 words
The RMS determining circuit of claim 1 wherein said m-bit ADDER provides an m+1 data bit to said m+1 bit latch.
Claim 6
Dependent Claim
33 words
The RMS determining circuit of claim 1 wherein said m+1 latch provides m data bits at said RMS output said m data bits being equivalent to the RMS value of said circuit current.
Claim 7
Dependent Claim
76 words
The RMS determining circuit of claim 1 including: a second divide-by-N counter, a second UP-counter, a second m+1 bit latch and a second m-bit adder electrically connected in parallel respectively with said divide-by-N counter, said UP-counter, said m+1 bit latch and said m-bit full adder, said second divide-by-N counter also being connected with a third predetermined frequency for providing a second data-bit at a second RMS output equivalent to the RMS value of said circuit current.
Claim 8
Dependent Claim
56 words
The RMS determining circuit of claim 6 wherein said full m-bit full adder comprises an 8-bit full adder and said second m-bit adder comprises an 11-bit full adder, said first data bit comprising an 8 data bit at said RMS output and said second data bit comprising an 11 data bit at said second RMS output.
References Cited (Backward Citations)
US3885134A
Cited
US4199719A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-04-26 | 1991-10-26 | 1992-04-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-04-26 | 1995-10-26 | 1996-04-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-04-26 | 1999-10-26 | 2000-04-26 | $7700.00 | Window Closed / Lapsed |