Method of controlling a microprocessor to monitor input signals at irregular mutually intersecting intervals

Claim 2

Method of controlling a microprocessor having a program, data processing circuits including at least one accumulator, random access memory means of which a portion is constituted as a multiplicity of plural-bit storage registers, means for writing data into and reading data out of said registers under program control, a clock frequency source and clocking connections, interrupt and reset inputs and input and output ports respectively for a plurality of input signals and a plurality of output signals, said method serving for controlling said microprocessor in operations thereof which require taking input signals respectively at said input ports at irregular mutually intersecting intervals for initiation thereby of time-critical brief program routines and comprising the steps of: assigning in said random access memory at least one said storage register for each of a plurality of said input signals present respectively at said input ports, each of said assigned registers having a carry out state recognizable by said microprocessor; generating timing signals at a constant frequency substantially lower than said microprocessor clock frequency and using all of said timing signals as interrupt signals supplied to said interrupt input of said microprocessor for initiating a time-critical routine of altering the numerical content of each of said assigned registers; immediately after the appearance, at said interrupt input, of each of said interrupt signals supplied at regular intervals, performing for at least one of a first portion of said assigned registers, the substeps of: determining whether a first input signal (G) of said input signals is in a predetermined one of two possible states thereof after having been in the other of said two states right after the last previous one of said interrupt signals; in the event when said first input signal is in said one predetermined state and was in said other state right after the last previous one of said interrupt signals, writing in a predetermined initial content value in said at least one of said first portion of said assigned registers; in all other cases, determining whether said at least one register is in a carry out state; if so, producing a change of state in one of said output signals at one of said output ports and if not, transferring the content of said at least one register to an accumulator of said microprocessor, altering the value of said content of said at least one register by one unit in a predetermined direction of alteration and transferring said altered content to said at least one register; and thereafter returning the operation of said microprocessor to said program thereof at the stage of said program reached at the time of the said interrupt signal which initiated the substeps above recited.

Claim 3

Method according to claim 1, wherein said substeps preceding the return to said program further include: reading at least one (21) of a second portion of said assigned registers if a second input signal (P) of said input signals is in a first predetermined state of two possible states thereof after having been in the second of said two states right after the last previous one of said interrupt signals; and resetting said at least one (21) register of said second portion of said assigned registers if said second input signal (P) of said input signals is in said second state thereof after having been in said first state thereof right after the last previous one of said interrupt signals.

Claim 4

Method according to claim 1 wherein, for at least one (15, 16) of said first portion (15-18) of said assigned registers, the substep which begins with determining whether a register is in a carry out state is performed, in the event said register is in a carry out state, with the addition of a substep of writing into said register a predetermined count value content.

Claim 5

Method according to claim 3 wherein said substep of writing in a predetermined count value content into said at least one register (15, 16) is performed by writing in different first and second count values in alternation in successive routines respectively initiated by successive interrupt signals supplied at regular intervals and wherein the recognition of said carry out state of said at least one register is used for timing the duration of a particular state of a corresponding one of said output signals and the length of an interval between successive occurrences of said particular state thereof.

Claim 6

Method according to claim 4, wherein said substeps performed prior to return to said program further include: determining whether a first input signal (G) of said input signals is in a predetermined first state of two possible states thereof; if said first input signal is in said first state, transferring the content of a first register (19) of a second portion of said assigned registers to an accumulator of said microprocessor, altering the value of said register content by one unit in a predetermined direction of alteration and transferring said altered content to said first register (19); determining whether said first input signal (G) is in the second of its two possible states after having been in said first state thereof right after the last previous interrupt signal of said interrupt signals supplied at regular intervals and in that event reading out and storing the content of said first register (19) followed by restoring the content of said register to a predetermined initial count value content; and wherein said program provides first and second limit values of the content read out of said first register (19) and provides for comparing said stored read out content of said first register after return of said microprocessor to said program and further provides, in response to the said comparing step, for reducing the frequency of said timing signals when said first limit value is reached after previous read out values lying between said limit values and for increasing the frequency of said timing signals when said second limit value is reached after previous readout values lying between said limit values.

Claim 7

Method according to claim 5 in which the step of reducing the frequency of said timing signals is performed by halving said frequency and the step of increasing said frequency is performed by doubling said frequency.

Claim 8

Method according to claim 5, wherein the step of increasing said frequency is made subject to an upper limit of said frequency.

Claim 9

Method according to claim 6, wherein said frequency of said timing signals is derived from the clock frequency of said microprocessor.

Claim 10

Method according to claim 1, wherein said frequency of said timing signals is derived from the clock frequency of said microprocessor.

Claim 11

Method of controlling a microprocessor having program, data processing circuits including at least one accumulator, random access memory means of which a portion is constituted as a multiplicity of plural-bit storage registers, means for writing data into and reading data out of said registers under program control, a clock frequency source and clocking connections, interrupt and reset inputs and input and output ports respectively for a plurality of input signals and a plurality of output signals, said method serving for controlling said microprocessor in operations thereof which require taking input signals respectively at said input ports at irregular mutually intersecting intervals for initiation thereby of time-critical brief program routines and comprising the steps of: assigning in said random access memory at least one said storage register for each of a plurality of said input signals present respectively at said input ports; each of said assigned registers having a carry out state recognizable by said microprocessor; generating timing signals at a constant frequency substantially lower than said microprocessor clock frequency and using all of said timing signals as interrupt signals supplied to said interrupt input of said microprocessor for initiating a time-critical routine of altering the numerical content of each of said assigned registers; immediately after the appearance, at said interrupt input, of each of said interrupt signals supplied at regular intervals, performing, for at least one of a first portion of said assigned registers, the substeps of: determining whether said at least one of said first portion of said assigned registers is in a carry out state, if so, producing a change of state in one of said output signals at one of said output ports and if not, transferring the content of said at least one register to an accumulator of said microprocessor, altering the value of said content of said at least one of said first portion of said assigned registers by one unit in a predetermined direction of alteration and transferring said altered content to said at least one of said first portion of said assigned registers; and reading at least one (21) of a second portion of said assigned registers if a second input signal (P) of said input signals is in a first predetermined state of two possible states thereof after having been in the second of said two states right after the previous one of said interrupt signals; resetting said at least one (21) register of said second portion of said assigned registers if said second input signal (P) of said input signals is in said second state thereof after having been in said first state thereof right after the last previous one of said interrup signals; and thereafter returning the operation of said microprosessor to said program thereof at the stage of said program reached at the time of the said interrupt signal which initiated the substeps above recited.

Claim 12

Method of controlling a microprocessor having program, data processing circuits including at least one accumulator, random access memory means of which a portion is constituted as a multiplicity of plural-bit storage registers, means for writing data into and reading data out of said registers under program control, a clock frequency source and clocking connections, interrupt and reset inputs and input and output ports respectively for a plurality of input signals and a plurality of output signals, said method serving for controlling said microprocessor in operations thereof which require taking input signals respectively at said input ports at irregular mutually intersecting intervals for initiation thereby of time-critical brief program routines and comprising the steps of: assigning in said random access memory at least one said storage register for each of a plurality of said input signals present respectively at said input ports; each of said assigned registers having a carry out state recognizable by said microprocessor; generating timing signals at a constant frequency substantially lower than said microprocessor clock frequency and using all of said timing signals as interrupt signals supplied to said interrupt input of said microprocessor for initiating a time-critical routine of altering the numerical content of each of said assigned registers; immediately after the appearance, at said interrupt input, of each of said interrupt signals supplied at regular intervals, performing, for at least one of a first portion of said assigned registers, the substeps of: determining whether said at least one of said first portion of said assigned registers is in a carry out state, if so, producing a change of state in one of said output signals at one of said output ports and if not, transferring the content of said at least one register to an accumulator of said microprocessor, altering the value of said content of said at least one of said first portion of said assigned registers by one unit in a predetermined direction of alteration and transferring said altered content to said at least one of said first portion of said assigned registers; and reading at least one (21) of a second portion of said assigned registers if a second input signal (P) of said input signals is in a first predetermined state of two possible states thereof after having been in the second of said two states right after the previous one of said interrupt signals; resetting said at least one (21) register of said second portion of said assigned registers if said second input signal (P) of said input signals is in said second state thereof after having been in said first state thereof right after the last previous one of said interrup signals; and thereafter returning the operation of said microprosessor to said program thereof at the stage of said program reached at the time of the said interrupt signal which initiated the substeps above recited.

Claim 13

Method according to claim 10, wherein said substeps performed prior to return to said program further includes: upon recognition that said at least one register of said first portion of said assigned registers is in a carry out state, writing in a predetermined count value content into said at least one register.

Claim 14

Method according to claim 11, wherein said substep of writing in a predetermined count value content into said at least one register is performed by writing in different first and second count values in alternation in successive routines respectively initiated by successive interrupt signals supplied at regular intervals and wherein the recognition of said carry out state of said at least one regiister is used for timing the duration of a particular state of a corresponding one of said output signals and the length of an interval between successive occurrences of said particular state thereof.

Claim 15

Method according to claim 12, wherein said substeps performed prior to return to said program further include: determining whether a first input signal (G) of said input signals is in a predetermined first state of two possible states thereof; if said first input signal is in said first state, transferring the content of a first register (19) of a second portion of said assigned registers to an accumulator of said microprocessor, altering the value of said register content by one unit in a predetermined direction of alteration and transferring said altered content to said first register (19); determining whether said first input signal (G) is in the second of its two possible states after having been in said first state thereof right after the last previous interrupt signal of said interrupt signals supplied at regular intervals and in that event reading out and storing the content of said first register (19) followed by restoring the content of said register to a predetermined initial count value content; and wherein said program provides first and second limit values of the content read out of said first register (19) and provides for comparing said stored read out content of said first register after return of said microprocessor to said program and further provides, in response to the said comparing step, for reducing the frequency of said timing signals when said first limit value is reached after previous read out values lying between said limit values and for increasing the frequency of said timing signals when said second limit value is reached after previous readout values lying between said limit values.

Claim 16

Method according to claim 13 in which the step of reducing the frequency of said timing signals is performed by halving said frequency and the step of increasing said frequency is performed by doubling said frequency.

Claim 17

Method according to claim 13, wherein the step of increasing said frequency is made subject to an upper limit of said frequency.

Claim 18

Method according to claim 13, wherein said frequency of said timing signals is derived from the clock frequency of said microprocessor.

Claim 19

Method according to claim 10, wherein said frequency of said timing signals is derived from the clock frequency of said microprocessor.