Field effect device maintaining a high speed operation in a high voltage operation

Claim 2

A field effect transistor comprising: a gate electrode applied with a gate voltage; an insulator film formed under said gate electrode; a channel-forming semiconductor region formed under said gate electrode in contact with said insulator film, said channel-forming semiconductor region primarily consisting of first and second semiconductor materials, said second semiconductor material having an electron affinity lower than said first semiconductor material, the content of said first semiconductor material in said channel-forming semiconductor region decreasing with distance from an upper surface thereof contacted with said insulator film, and said channel forming region forming a conductive channel in response to said gate voltage; and source and drain regions formed respectively on both sides of said channel-forming semiconductor region.

Claim 3

A field effect transistor as claimed in claim 1, wherein said first semiconductor material is selected from a group of InAs and GaP, and said second semiconductor material is selected from a group of GaAs and InP.

Claim 4

A field effect transistor as claimed in claim 2, wherein the content of said second semiconductor material increases with depth from zero at said upper surface, and the content of said first semiconductor material decreases with depth to thirty percent at a bottom of said channel-forming semiconductor region.

Claim 5

A field effect device comprising a channel forming region of a semiconductor material having an electron affinity which lowers in accordance with the depth from one surface thereof, an insulator material formed on said one surface and a control electrode formed on said insulator material, wherein said semiconductor material is selected from a group of Ga x In 1-x As and In x Ga 1-x P in which the mole ratio x increases as the depth from said surface increases.

Claim 6

A field effect device comprising a channel forming region of a semiconductor material having an electron affinity which lowers in accordance with the depth from one surface thereof, an insulator material formed on said one surface and a control electrode formed on said insulator material, wherein said semiconductor material is selected from a group of Ga x In 1-x As and In x Ga 1-x P in which the mole ratio x increases as the depth from said surface increases.

Claim 7

A field effect device comprising a channel forming region of a semiconductor material having an electron affinity which lowers in accordance with the depth from one surface thereof, an insulator material formed on said one surface and a control electrode formed on said insulator material, wherein said control electrode is a gate electrode and said field effect device further comprises source and drain regions formed on both sides of said channel forming region, respectively, and wherein said semiconductor material is selected from a group of Ga x In 1-x As and In x Ga 1-x P in which the mole ratio x increases as the depth from said one surface increases.

Claim 8

A field effect device comprising a channel forming region of a semiconductor material having an electron affinity which lowers in accordance with the depth from one surface thereof, an insulator material formed on said one surface and a control electrode formed on said insulator material, wherein said control electrode is a gate electrode and said field effect device further comprises source and drain regions formed on both sides of said channel forming region, respectively, and wherein said semiconductor material is selected from a group of Ga x In 1-x As and In x Ga 1-x P in which the mole ratio x increases as the depth from said one surface increases.

Claim 9

A field effect transistor comprising: a substrate of semi-insulating GaAs; a first semiconductor layer of pure AlAs formed on said substrate; a second semiconductor layer of a semiconductor material formed on said first semiconductor layer, said second semiconductor layer having a bottom surface contacting said first semiconductor layer and an upper surface, and said semiconductor material being Al x Ga 1-x As in which the mole ratio X increases from 0 at said upper surface to 1 at said bottom surface; source and drain regions separately formed in said second semiconductor layer to extend from said upper surface; a third semiconductor layer formed on and contacting said upper surface of said second semiconductor layer located between said source and drain regions, said third semiconductor layer being formed of AlGaAs doped with donor impurities; and a gate electrode formed on and contacting said third semiconductor layer.

Claim 10

A field effect transistor comprising: a substrate of semi-insulating GaAs; a first semiconductor layer of pure AlAs formed on said substrate; a second semiconductor layer of a semiconductor material formed on said first semiconductor layer, said second semiconductor layer having a bottom surface contacting said first semiconductor layer and an upper surface, and said semiconductor material being Al x Ga 1-x As in which the mole ratio X increases from 0 at said upper surface to 1 at said bottom surface; source and drain regions separately formed in said second semiconductor layer to extend from said upper surface; a third semiconductor layer formed on and contacting said upper surface of said second semiconductor layer located between said source and drain regions, said third semiconductor layer being formed of AlGaAs doped with donor impurities; and a gate electrode formed on and contacting said third semiconductor layer.

Claim 11

A field effect transistor comprising: a substrate of semi-insulating GaAs; a semiconductor layer formed on said substrate, said semiconductor layer having an upper surface on the side opposite said substrate, and said semiconductor layer being formed of Ga x In 1-x As in which the mole ratio x increases with depth from said upper surface from 0.3 to 1.0; source and drain regions separately formed in said semiconductor layer to extend from said upper surface; an insulator layer formed on said upper surface of said semiconductor layer located between said source and drain regions; and a gate electrode of metal formed on said insulator layer.

Claim 12

A field effect transistor comprising: a substrate of semi-insulating GaAs; a semiconductor layer formed on said substrate, said semiconductor layer having an upper surface on the side opposite said substrate, and said semiconductor layer being formed of Ga x In 1-x As in which the mole ratio x increases with depth from said upper surface from 0.3 to 1.0; source and drain regions separately formed in said semiconductor layer to extend from said upper surface; an insulator layer formed on said upper surface of said semiconductor layer located between said source and drain regions; and a gate electrode of metal formed on said insulator layer.