IC chip error detecting and correcting apparatus

Claim 1

Integrated circuit means for providing a predetermined processing of a plurality of input signals for producing a plurality of required output signals, said integrated circuit means comprising: a plurality of integrated circuit chips of like design, each chip providing a predetermined plurality of chip input terminals, a predetermined plurality of chip output terminals, and a predetermined chip processing capability for processing signals applied to the chip input terminals and for producing signals in response thereto at the chip output terminals; and means for providing different predetermined wiring arrangements for coupling said input signals to the chip input terminals of said integrated circuit chips such that the chip input terminals of one chip are coupled to said input signals in a different predetermined manner from the chip input terminals of the other chip; said different predetermined wiring arrangements being chosen in conjunction with said predetermined chip processing capability so that each chip produces different ones of said required output signals at its output terminals, the composite of the signals produced at the chip output terminals of said plurality of integrated circuit chips providing said required output signals; said plurality of integrated circuit chips comprising first and second integrated circuit chips of like design, wherein each chip includes error detecting and correcting means for providing error detecting and correcting of said input signals, wherein said input signals comprise input data bits and input check bits, wherein said input check bits have values determined based on an inversely symmetrical Hamming code, wherein said error detecting and correcting means operates to provide for performing detecting and correcting operations on said input bits based on said inversely symmetrical Hamming code.