IC chip error detecting and correcting method

Claim 1

A method employing integrated circuit chips for providing a predetermined processing of a plurality of input signals for producing a plurality of required output signals, wherein said input signals comprise input data bits and input check bits, and wherein said input check bits have values determined based on an inversely symmetrical Hamming code, said method comprising: providing first and second integrated circuit chips of of like design, each chip having a predetermined plurality of chip input terminals which is of sufficient number to receive all of said input signals, a predetermined plurality of chip output terminals which is of insufficient number to provide all of said required output signals, and a predetermined chip processing capability for processing signals applied to the chip input terminals and for producing signals in response thereto at the chip output terminals; and coupling said input signals to the chip input terminals of said integrated circuit chips in a different predetermined manner for each chip and processing the thus coupled inputs to said chips in a manner such that each chip produces different ones of said required output signals at its output terminals, the composite of the signals produced at the chip output terminals of said plurality of integrated circuit chips providing said required output signals; said processing including performing error detecting and correcting operations on each chip in response to the input bits coupled thereto based on said inversely symmetrical Hamming code.

Claim 2

A method employing integrated circuit chips for providing a predetermined processing of a plurality of input signals for producing a plurality of required output signals, wherein said input signals comprise input data bits and input check bits, and wherein said input check bits have values determined based on an inversely symmetrical Hamming code, said method comprising: providing first and second integrated circuit chips of of like design, each chip having a predetermined plurality of chip input terminals which is of sufficient number to receive all of said input signals, a predetermined plurality of chip output terminals which is of insufficient number to provide all of said required output signals, and a predetermined chip processing capability for processing signals applied to the chip input terminals and for producing signals in response thereto at the chip output terminals; and coupling said input signals to the chip input terminals of said integrated circuit chips in a different predetermined manner for each chip and processing the thus coupled inputs to said chips in a manner such that each chip produces different ones of said required output signals at its output terminals, the composite of the signals produced at the chip output terminals of said plurality of integrated circuit chips providing said required output signals; said processing including performing error detecting and correcting operations on each chip in response to the input bits coupled thereto based on said inversely symmetrical Hamming code.