Serial data bus for serial communication interface (SCI), serial peripheral interface (SPI) and buffered SPI modes of operation

Claim 1

A communication system for the transmission of data messages through a data bus between two or more user microprocessors coupled to the data bus, the user microprocessors having any one of the following interface ports; a serial communications interface (SCI) port, a serial peripheral interface (SPI) port or a buffered serial peripheral interface (BSPI) port along with a clock port and an input/output port, the user microprocessors being coupled to the data bus by a bus interface integrated circuit, the bus interface integrated circuit comprising: a reset circuit; an arbitration detector; a buffer; a collision detector; a bus driver; a bus receiver; an idle detector; a series circuit formed by the connection of the arbitration detector, collision detector and bus driver connected between the interface port of the user microprocessor and the data bus to transmit data from the user microprocessor to the data bus; the bus receiver connected between the data bus and the interface port of the user microprocessor to receive data messages from the data bus to the user microprocessor; the idle detector comprising an idle counter and idle flip-flop connected betwen the input/output port of the user microprocessor and individually to the arbitration detector and collision detector to monitor the data bus and detect when the data bus is idle and when the data bus is busy; a digital filter connected between the bus receiver and the SCI Port of the user microprocessor to filter out noise from the data messages before being processed by other parts of the bus interface integrated circuit; timing and synchronizing means to establish synchronizing and a baud rate timing signal for use by the arbitration detector, collision detector and idle detector comprising: a start/stop bit generator to generate start and stop bits; a clock divider to receive a clock pulse from the user microprocessor to generate a clock signal; a word counter to accept the clock signal and present timing and synchronizing information to the arbitration detector and to the collision detector; a start bit detector to count and indicate when a start bit signal and level is present on the data bus; a framing error detector to indicate when the stop bit level is not on the data bus at stop bit time; the idle detector to monitor and indicate when the data bus is in an idle condition; the bus interface integrated circuit being able to receive data from a user microprocessor configured for data communications in SCI, SPI or BSPI modes the bus interface integrated circuit further comprising: a mode select circuit for controlling data and shift clock (SCK) signal flow into and out of the bus interface integrated circuit by responding to the particular interface of the user microprocessor and operating in accordance with that interface, SCI, SPI or BSPI; an SCK selector for directing data in the buffered SPI mode and for describing the source of the clock signal for the buffer; an SCK counter to count SCK pulses from the user microprocessor; a byte counter for counting the number of bytes received; an SPI clock generator to generate SCK pulses to the user microprocessor and buffer; an SPI transmit scheduler and controller to control when data from a user microprocessor is put onto the bus in the SPI or BSPI modes; and a current source and a current sink to drive the logical condition of the bus in response to signals from the bus driver and the bus receiver of the bus interface integrated circuit associated with each user microprocessor on the bus.