Digital-to-analog converting system

Claim 2

A digital-to-analog converting system for converting a digital code having higher order bits and lower order bits to an analog value comprising: a divider (2) for dividing input digital codes into higher order bits adn lower order bits; a PAM controller (3) producing a PAM control signal (S PAM ) corresponding to said higher order bits for converting said higher order bits to a higher analog value in a first converting style; a current source (14, 15, 16) for generating a higher analog value corresponding to said PAM control signals; a digital-to-analog converter (4) for converting said lower order bits to a lower analog value in a second converting style using pulse width modulation means, and producing an analog value which is inferior to that produced in the first converting style in linearity, said pulse width modulation means including means for generating pulses having a plurality of different pulse widths and defining a conversion period, means for generating the two's complement of said lower order bits, and means for selecting pulses of different pulse width according to said lower order bits and said two's complement of said lower order bits, and logic means connected to said means for generating pulses and receiving selected pulses of different pulse widths from said means for selecting for producing an output signal formed of two different pulse width modulated waves in which said two pulse width modulated waves are arranged in respective first and second intervals of said conversion period and in which widths of said two pulse width modulated waves pulses vary symmetrically relative to respective central time points of said first and second intervals of said convertion period, thereby to improve linearity; and an adder (20) for adding together said higher and lower analog values.

Claim 3

A digital-to-analog converting system according to claim 1, wherein said first digital-to-analog converter converts said higher order bits to said higher analog value through Pulse Amplitude Modulation (PAM) providing a pulse level corresponding to said higher order bits.

Claim 4

A digital-to-analog converting system according to claim 1, wherein said means for selecting said pulses selects respective pulses in the first and second halves of one sampling period such that distortion due to the pulses selected in said first half of period is complementarily cancelled by the distortion due to pulses selected in said second half of period.

Claim 5

A digital-to-analog converting system according to claim 1, wherein said means for selecting said pulses generates pulses of pulse widths corresponding to bits, said pulses being dispersed as a plurality of pulses in one sampling period.

Claim 6

A digital-to-analog converting system for converting a digital code having higher order bits to an analog value comprising: a divider (2) for dividing input digital codes into higher order bits and lower order bits; a PAM controller (3) for producing a PAM control signal (S PAM ) corresponding to said higher order bits; a first current source (14, 15, 16) for generating a higher analog value corresponding to said PAM control signal; a PWM controller (4) for producing a PWM control signal (S PWM ) corresponding to said lower order bits and including a pulse width modulation means further comprising means for generating pulses having a plurality of different pulse widths and defining a conversion period, means for generating the two's complement of said lower order bits, and means for selecting pulses of different pulse width according to said lower order bits and said two's complement of said lower order bits, and logic means receiving selected pulses of different pulse widths from said means for selecting and connected to said means for generating pulses for producing an output signal formed of two different pulse width modulated waves arranged in two respective intervals of said conversion period, in which widths of said pulses in said output signal formed of said two pulse width modulated waves vary symmetrically relative to central time points of respective ones of said two intervals of said conversion period, thereby to improve linearity; a second current source (18) for generating a lower analog value corresponding to said PWM control signal; and an adder (20) for adding together said higher and lower analog values.

Claim 7

A digital-to-analog converting system for converting a digital code having higher order bits to an analog value comprising: a divider (2) for dividing input digital codes into higher order bits and lower order bits; a PAM controller (3) for producing a PAM control signal (S PAM ) corresponding to said higher order bits; a first current source (14, 15, 16) for generating a higher analog value corresponding to said PAM control signal; a PWM controller (4) for producing a PWM control signal (S PWM ) corresponding to said lower order bits and including a pulse width modulation means further comprising means for generating pulses having a plurality of different pulse widths and defining a conversion period, means for generating the two's complement of said lower order bits, and means for selecting pulses of different pulse width according to said lower order bits and said two's complement of said lower order bits, and logic means receiving selected pulses of different pulse widths from said means for selecting and connected to said means for generating pulses for producing an output signal formed of two different pulse width modulated waves arranged in two respective intervals of said conversion period, in which widths of said pulses in said output signal formed of said two pulse width modulated waves vary symmetrically relative to central time points of respective ones of said two intervals of said conversion period, thereby to improve linearity; a second current source (18) for generating a lower analog value corresponding to said PWM control signal; and an adder (20) for adding together said higher and lower analog values.

Claim 8

A digital-to-analog converting system according to claim 5, wherein said first current source consists of a plurality of current sources corresonding in number to the number of said higher order bits and having respective preset output current levels I, 2I, 4I,. . ., 2 n I (I being a reference current level, n being a positive integer).

Claim 9

A digital-to-analog converting system according to claim 6, wherein the current level of the minimum current source among said first current sources is equal to the current level of said second current source.

Claim 10

A digital-to-analog converting system for converting a digital code having higher order bits, middle order bits and lower order bits to an analog value comprising: a divider (25) for dividing input digital codes into higher order bits, middle order bits and lower order bits; a first digital-to-analog converter (30) including a PAM controller (3) for producing a PAM control signal (S PAM ) corresponding to said higher order bits for converting said higher order bits to a higher analog value in a first converting style; a current source for generating a higher analog value corresponding to said PAM control signal; a second digital-to-analog converter (40A) for converting said middle order bits to a middle analog value in a second converting style which is inferior to the first converting style in linearity; a third digital-to-analog converter (40B) for converting said lower order bits to a lower analog value in said second converting style; an adder (20) for adding together said higher, middle and lower analog values; and said second and third digital-to-analog converters each include a pulse width modulation means, each said pulse width modulation means further including means for generating pulses having a plurality of different pulse widths and defining a conversion period, means for generating the two's complement of said lower order bits, and means for selecting pulses of different pulse width according to said lower order bits and said two's complement of said lower order bits, and each including logic means connected to said means for generating pulses and receiving selected pulses of different pulse widths from said means for selecting for producing an output signal formed of two different pulse width modulated waves in which said two pulse width modulated waves are respectively arranged in two intervals of said conversion period and in which widths of said pulses in said output signal vary symmetrically relative to central time points of said two intervals within said conversion period, thereby to improve linearity.

Claim 11

A digital-to-analog converting system for converting a digital code having higher order bits, middle order bits and lower order bits to an analog value comprising: a divider (25) for dividing input digital codes into higher order bits, middle order bits and lower order bits; a first digital-to-analog converter (30) including a PAM controller (3) for producing a PAM control signal (S PAM ) corresponding to said higher order bits for converting said higher order bits to a higher analog value in a first converting style; a current source for generating a higher analog value corresponding to said PAM control signal; a second digital-to-analog converter (40A) for converting said middle order bits to a middle analog value in a second converting style which is inferior to the first converting style in linearity; a third digital-to-analog converter (40B) for converting said lower order bits to a lower analog value in said second converting style; an adder (20) for adding together said higher, middle and lower analog values; and said second and third digital-to-analog converters each include a pulse width modulation means, each said pulse width modulation means further including means for generating pulses having a plurality of different pulse widths and defining a conversion period, means for generating the two's complement of said lower order bits, and means for selecting pulses of different pulse width according to said lower order bits and said two's complement of said lower order bits, and each including logic means connected to said means for generating pulses and receiving selected pulses of different pulse widths from said means for selecting for producing an output signal formed of two different pulse width modulated waves in which said two pulse width modulated waves are respectively arranged in two intervals of said conversion period and in which widths of said pulses in said output signal vary symmetrically relative to central time points of said two intervals within said conversion period, thereby to improve linearity.