DC motor adaptive controller apparatus

Claim 2

An improvement for a regulator of the type having phase control of electric current supplied to a load from silicon controlled rectifier power semiconductors arranged in a bridge comprising: (a) a first dedicated analog and digital logic circuit means for determining whether said current is in discontinuous or continuous conduction from phase to phase of said semiconductors; and (b) a second dedicated analog and digital logic circuit means for operating said regulator at: (i) a first gain when said current is discontinuous, (ii) a second gain when said current is continuous, and (iii) a third gain when said current has a transition value when going from discontinuous to continuous conduction.

Claim 3

The improvement of claim 1 wherein said first circuit means further comprises a free-running digital clock signal and a digital counter which counts up said digital clock signal to a value representative of said current when said current is discontinuous and said first circuit means determines said transition value is above the value previously stored in said counter.

Claim 4

The improvement of claim 2 wherein said counter counts down said digital clock signal to a value representative of said current when said current is continuous and said first circuit means determines said transition value is below the value previously stored in said counter.

Claim 5

The improvement of claim 1 wherein said first circuit means further comprises: (a) a current transducer providing an instantaneous current feedback signal representative of bridge current; (b) a current detector comparator receiving said instantaneous current feedback signal and providing a digital output having a first value representative of the presence of bridge current and a second value representative of the absence of bridge current; (c) a D-type flip-flop receiving the output of said current detector comparator and clocked at a time immediately prior to each gate pulse command for phase-firing said bridge and having an output indicative of the discontinuous or continuous status of said current.

Claim 6

In a closed-loop SCR phase-controlled current regulator of the type having analog current reference and current feedback signals for regulating phase-controlled current in discontinuous conduction at relatively low current levels and in continuous conduction at relatively high current levels, the improvement comprising a free-running digital clock signal and a digital up/down counter gated to count said digital clock signal such that said counter contains a value representative of the highest level of phase-controlled current in discontinuous conduction and a dedicated analog and digital logic circuit means for operating said regulator at: (i) a first gain when the value stored in said counter is greater than the present value of said current reference signal, and (ii) a second gain when the value stored in said counter is less than the present value of said current reference signal.

Claim 7

In a closed-loop SCR phase-controlled current regulator of the type having analog current reference and current feedback signals for regulating phase-controlled current in discontinuous conduction at relatively low current levels and in continuous conduction at relatively high current levels, the improvement comprising a free-running digital clock signal and a digital up/down counter gated to count said digital clock signal such that said counter contains a value representative of the highest level of phase-controlled current in discontinuous conduction and a dedicated analog and digital logic circuit means for operating said regulator at: (i) a first gain when the value stored in said counter is greater than the present value of said current reference signal, and (ii) a second gain when the value stored in said counter is less than the present value of said current reference signal.

Claim 8

The improvement of claim 5 wherein said counter is further gated for decrementing to and thereafter storing a value representative of the lowest level of phase-controlled current in continuous conduction.

Claim 9

Apparatus for operating a regulator in a closed-loop current control mode by adjusting the firing angle of power semiconductors arranged in a bridge circuit between a source of alternating current input power and a DC motor armature comprising: (a) a current transducer for providing a feedback signal representative of the instantaneous value of motor current; (b) a low-pass filter for averaging said instantaneous current feedback signal to provide a signal representative of average motor current; (c) a digital sample and hold circuit including a first comparator receiving said average motor current signal and a dual-gated up/down counter adapted to increment and decrement in response to a respective one of two gating signals and a digital-to-analog converter for providing an analog signal representative of the contents of said counter; and (d) a second comparator receiving said instantaneous motor current feedback signal and providing an output representative of the zero or non-zero condition of said instantaneous current feedback signal to a D-type flip-flop receiving a clock signal immediately prior to the firing signal in each phase of the bridge circuit wherein said counter is gated by an increment enable gate responsive to a high output of said first comparator to increment said counter when the average value of said motor current signal exceeds the value stored in said counter and said D-type flip-flop indicates that said bridge current is discontinuous.

Claim 10

Apparatus for operating a regulator in a closed-loop current control mode by adjusting the firing angle of power semiconductors arranged in a bridge circuit between a source of alternating current input power and a DC motor armature comprising: (a) a current transducer for providing a feedback signal representative of the instantaneous value of motor current; (b) a low-pass filter for averaging said instantaneous current feedback signal to provide a signal representative of average motor current; (c) a digital sample and hold circuit including a first comparator receiving said average motor current signal and a dual-gated up/down counter adapted to increment and decrement in response to a respective one of two gating signals and a digital-to-analog converter for providing an analog signal representative of the contents of said counter; and (d) a second comparator receiving said instantaneous motor current feedback signal and providing an output representative of the zero or non-zero condition of said instantaneous current feedback signal to a D-type flip-flop receiving a clock signal immediately prior to the firing signal in each phase of the bridge circuit wherein said counter is gated by an increment enable gate responsive to a high output of said first comparator to increment said counter when the average value of said motor current signal exceeds the value stored in said counter and said D-type flip-flop indicates that said bridge current is discontinuous.

Claim 11

The apparatus of claim 7 further comprising a decrement enable gate responsive to a low output of said first comparator to decrement said counter while said D-type flip-flop indicates said motor current is continuous and the value stored in said counter exceeds the average value of said motor current signal.