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US4738683A Expired / Lapsed US ⏱️ 0.0 years remaining

Method of fabrication of gates for integrated circuits

Assignee: Thales SA
•
Filing: 1985-10-30
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Granted: 1988-04-19
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Expires: 2005-10-30
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Abstract

Abstract In order to fabricate gates for an integrated circuit formed on a semiconductor substrate of silicon covered with at least one layer of oxide, one layer of polycrystalline silicon and if necessary one layer of silicide, an initial step consists in successive deposition of a silicon nitride layer and a silicon oxide layer, openings in these two layers being then formed by photoetching in a second step. In a third step, the silicon oxide layer is partly removed by deoxidation in order to bare the nitride layer over a certain distance which determines the spacing between two consecutive gates, oxide being then grown within the openings formed during the second step. The final step consists in removing the nitride regions uncovered during the third step as well as the subjacent silicide layer if this latter is provided and the subjacent polycrystalline silicon layer.

Inventors

  • 👤 Pierre Blanchard
  • 👤 Jean P. Cortot

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-29 22:52
CPC Classifications
H; H10; H10D; H10D44/00; H10D44/01; H10D44/041; H10P; H10P76/00; H10P76/40; H10P76/408; H10P76/4085; Y; Y10; Y10S; Y10S148/00; Y10S148/05; Y10S148/051; Y10S148/111; Y10S438/00; Y10S438/911

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 151 words
A method of fabrication of gates for an integrated circuit formed on a semiconductor substrate of silicon covered with at least one contiguous layer of oxide, one layer of polycrystalline silicon and if necessary one layer of silicide, comprising the following steps: (1) successive deposition of a layer of silicon nitride and a layer of silicon oxide over the covered substrate; (2) formation of openings in said two last-mentioned layers by etching; (3) partial removal of the remainder of the silicon oxide layer by etching in order to uncover the nitride layer over a desired distance which determines the spacing betwen two consecutive gates; (4) growth of oxide selectively within the openings formed during the second step; and (5) removal of the nitride regions uncovered during the third step as well as any subjacent layer of silicide, and the subjacent layer of polycrystalline silicon to expose the contiguous layer of oxide.
Claim 2
Independent Claim 151 words
A method of fabrication of gates for an integrated circuit formed on a semiconductor substrate of silicon covered with at least one contiguous layer of oxide, one layer of polycrystalline silicon and if necessary one layer of silicide, comprising the following steps: (1) successive deposition of a layer of silicon nitride and a layer of silicon oxide over the covered substrate; (2) formation of openings in said two last-mentioned layers by etching; (3) partial removal of the remainder of the silicon oxide layer by etching in order to uncover the nitride layer over a desired distance which determines the spacing betwen two consecutive gates; (4) growth of oxide selectively within the openings formed during the second step; and (5) removal of the nitride regions uncovered during the third step as well as any subjacent layer of silicide, and the subjacent layer of polycrystalline silicon to expose the contiguous layer of oxide.
Claim 3
Dependent Claim 18 words
A method in accordance with claim 1, wherein the silicon oxide layer is deposited in the vapor phase.
Claim 4
Dependent Claim 24 words
A method in accordance with claim 1, wherein the openings are formed either by the chemical etching process or by the dry plasma-etching process.
Claim 5
Dependent Claim 29 words
A method in accordance with claim 1, wherein removal of the uncovered nitride regions is carried out either by the chemical etching process or by the dry plasma-etching process.

References Cited (Backward Citations)

US4063992A Cited
US4083098A Cited
GB2111304A Cited
EP0098652A2 Cited
US4514251A Cited
EP0132009A2 Cited
US4574468A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1991-04-19 1991-10-19 1992-04-19 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1995-04-19 1995-10-19 1996-04-19 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1999-04-19 1999-10-19 2000-04-19 $7700.00 Window Closed / Lapsed

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