Processor

Claim 2

A processor comprising: a central processing unit (CPU), a local memory and a local input/output (I/O) device which are coupled to an internal bus, an input/output (I/O) interface adapted to couple said internal bus to a system bus external to the processor, said CPU being adapted to output an address signal when it is about to access a device external to said CPU, said I/O device being adapted to access said internal memory through said internal bus, and a system bus access controller including: first means for receiving said address signal output from said CPU and transmitting a system bus use request (SBUR) signal to said system bus without using said internal bus when said address signal designates an access to a device external to the processor; and second means for receiving said system bus use request (SBUR) signal from said first means and a system bus use acknowledgment (SBUA) signal from said system bus, said second means operating to put said CPU in a HOLD condition after said system bus use request (SBUR) signal is transmitted until said system bus use acknowledgment (SBUR) signal is received, thereby permitting said local memory, said local input/output device, or said input/output interface to utilize said internal bus when said CPU is in said HOLD condition.

Claim 3

A processor as set forth in claim 1 wherein said CPU includes a CPU internal bus, a timing controller, a group of registers coupled to said CPU internal bus, and an address buffer coupled to said register group and adapted to supply said address signal to said internal bus of the processor, and wherein said first means includes an address table storing a discrimination information for an external address, and a comparator adapted to compare said address in said address buffer with the address discrimination information in said address table and to output said system bus use request (SBUR) signal to said system bus when said address signal designates access to a device external to the processor, and said second means includes a gate means for receiving said SBUR signal and said SBUA signal so as to output a HOLD signal to said timing controller after said SBUR signal is generated until said SBUA signal is received, thereby putting said CPU in said HOLD condition.

Claim 4

A processor as set forth in claim 2 wherein said system bus access controller further includes a buffer register having an input coupled to the output of said comparator and an output coupled to said system bus, thereby supplying said SBUR signal stored in said buffer register to said system bus.

Claim 5

A processor as set forth in claim 2 wherein said gate means is composed of an AND gate having a non-inverted input coupled to the output of said comparator and an inverted input connected to said system bus so as to receive said system bus use acknowledgment (SBUA) signal from said system bus, so that said AND gate enables said HOLD signal when the output of said comparator is enabled and said SBUA signal is in a disabled condition.

Claim 6

A processor as set forth in claim 4 wherein when said system bus use acknowledgment (SBUA) signal is input, said AND gate disables said HOLD signal so that said CPU goes out of the HOLD condition so as to supply to said I/O interface at least the address signal stored in said address buffer just before said CPU entered the HOLD condition.

Claim 7

A processor as set forth in claim 5 wherein said I/O interface includes a bus buffer coupled between said internal bus of said processor and said system bus, a decoder having an input coupled to said internal bus of said processor for receiving at least a portion of said address signal and said control signal supplied from said CPU so as to supply a trigger signal to said bus buffer, and a second gate means in response to said trigger signal to generate and supply a WAIT signal to said CPU through said internal bus of said processor.

Claim 8

A multiprocessor system comprising: a plurality of processors, a common memory, a bus arbiter, and a system bus coupled to said processors, said common memory and said bus arbiter, each of said processors including a central processing unit (CPU), a local memory and a local input/output (I/O) device which are coupled to an internal bus, and an input/output (I/O) interface adapted to couple said internal bus to said system bus which is external to said processors, said CPU being adapted to output an address signal when it is about to access a device external to said CPU, said (I/O) device being adapted to access said internal memory through said internal bus, wherein at least one processor also comprises a system bus access controller including first means for receiving said address signal output from said CPU and transmitting a system bus use request (SBUR) signal through said system bus to said bus arbiter when said address signal designates an access to a device external to the processor; and second means receiving said system bus use request (SBUR) signal from said first means and a system bus use acknowledgment (SBUA) signal through said system bus from said bus arbiter, said second means operating to put said CPU in a HOLD condition after said system bus use request (SBUR) signal is transmitted until said system bus use acknowledgment (SBUA) signal is received from said bus arbiter, thereby permitting said local memory, said local input/output device, or said input/output interfere to utilize said internal bus when said CPU is in said HOLD condition.

Claim 9

A multiprocessor system comprising: a plurality of processors, a common memory, a bus arbiter, and a system bus coupled to said processors, said common memory and said bus arbiter, each of said processors including a central processing unit (CPU), a local memory and a local input/output (I/O) device which are coupled to an internal bus, and an input/output (I/O) interface adapted to couple said internal bus to said system bus which is external to said processors, said CPU being adapted to output an address signal when it is about to access a device external to said CPU, said (I/O) device being adapted to access said internal memory through said internal bus, wherein at least one processor also comprises a system bus access controller including first means for receiving said address signal output from said CPU and transmitting a system bus use request (SBUR) signal through said system bus to said bus arbiter when said address signal designates an access to a device external to the processor; and second means receiving said system bus use request (SBUR) signal from said first means and a system bus use acknowledgment (SBUA) signal through said system bus from said bus arbiter, said second means operating to put said CPU in a HOLD condition after said system bus use request (SBUR) signal is transmitted until said system bus use acknowledgment (SBUA) signal is received from said bus arbiter, thereby permitting said local memory, said local input/output device, or said input/output interfere to utilize said internal bus when said CPU is in said HOLD condition.

Claim 10

A multiprocessor system as set forth in claim 7 wherein said CPU of said one processor includes a CPU internal bus, a timing controller, a group of registers coupled to said CPU internal bus, and an address buffer coupled to said register group and adapted to supply said address signal to said internal bus of the processor, and wherein said first means includes an address table storing a discrimination information for an external address, and a comparator adapted to compare said address in said address buffer with the address discrimination information in said address table and to output said system bus use request (SBUR) signal to said system bus when said address signal designates access to a device external to the processor, and said second means includes a gate means for receiving said SBUR signal and said SBUA signal so as to output a HOLD signal to said timing controller after said SBUR signal is generated until said SBUA signal is received, thereby putting said CPU in said HOLD condition.

Claim 11

A multiprocessor system as set forth in claim 8 wherein said system bus access controller further includes a buffer register having an input coupled to the output of said comparator and an output coupled to said system bus, thereby supplying said SBUR signal stored in said buffer register through said system bus to said bus arbiter.

Claim 12

A multiprocessor as set forth in claim 8 wherein said gate means is composed of an AND gate having a non-inverted input coupled to the output of said comparator and an inverted input connected to said system bus so as to receive said system bus use acknowledgment (SBUA) signal transmitted through said system bus from said bus arbiter, so that said AND gate enables said HOLD signal when the output of said comparator is enabled and said SBUA signal is in a disabled condition.

Claim 13

A multiprocessor system as set forth in claim 10 wherein when said one processor receives said system bus use acknowledgment (SBUA) signal, said AND gate of said processor disables said HOLD signal so that said CPU goes out of the HOLD condition so as to supply to said I/O interface at least the address signal stored in said address buffer just before said CPU entered the HOLD condition.

Claim 14

A multiprocessor system as set forth in claim 11 wherein said I/O interface of said CPU of said one processor includes a bus buffer coupled between said internal bus of said processor and said system bus, a decoder having an input coupled to said internal bus of said processor for receiving at least a portion of said address signal supplied from said CPU so as to supply a trigger signal to said bus buffer, and a second gate means in response to said trigger signal to generate and supply a WAIT signal to said CPU through said internal bus of said processor.

Claim 15

A multiprocessor system as set forth in claim 12 wherein said second gate means is composed of a second AND gate having a non-inverted input coupled to the output of said decoder and an inverted input connected to said system bus to receive an access completion signal when the access to the external of the processor is completed, said second gate operating to disable said WAIT signal at the receipt of said access completion signal so that said CPU goes out of said WAIT condition so as to carry out the next operation.

Claim 16

A multiprocessor system as set forth in claim 7, wherein said CPU of said at least one processor further includes third means for releasing said internal bus from said CPU during the period of time from the moment said system bus use request signal is generated until said system bus use acknowledgment signal is received from said bus arbiter, so that at least said local input/output device can perform an access directly to said local memory during said period of time.