Process for the simultaneous production of self-aligned bipolar transistors and complementary MOS transistors on a common silicon substrate

Claim 1

In a process for the simultaneous production of self-aligned bipolar transistors and complementary MOS transistors on a common p-doped silicon substrate wherein n-doped regions are produced in said p-doped substrate and insulated npn-bipolar transistors are formed into said n-doped regions, said n-regions forming the collectors of said bipolar transistors, the sequence of steps in the following order: (a) applying a double layer of silicon oxide and silicon nitride onto said p-doped substrate, and structuring said silicon nitride layer for subsequent local oxidation, (b) locally oxidizing said substrate to form field oxide zones for separation of the active transistor regions to be formed, using said silicon nitride layer as a mask, (c) implanting n- and p-doping ions in said substrate with diffusion, (d) removing the nitride/oxide mask, (e) applying a first insulating layer of a thickness not exceeding 50 nm over the full area of said substrate to serve as a protective layer for the later formed gate zones during etching, serve as a dielectric for storage capacitors formed in said substrate, and prevent diffusion of boron from a subsequently applied p-conducting layer in portions of said bipolar transistors which are adjacent to the later formed collector zones, (f) removing said first insulating layer in the portions other than those to form the collector zones of the bipolar transistors, utilizing a photo-resist mask, (g) removing said photo-resist mask, (h) implanting a dopant to form the electrodes of said storage capacitor utilizing a photo-resist mask, (i) depositing a p-conducting layer of polysilicon, a refractory metal silicide or a double layer of polysilicon and refractory metal silicide over the full area of said substrate, (j) applying a second insulating layer over said full area, (k) dry etching said p-conducting layer and said second insulating layer by a photo-resist process to form vertical sidewalls, said etching extending down to said substrate for defining the base zones of the bipolar transistors and the storage capacitor zones, implanting channel zones in said MOS transistors, (m) implanting boron by a photo-resist process to produce active base zones, (n) depositing a third insulating layer over the edges of the structures of the p-conducting layer and said second insulating layer, (o) anisotropically etching the resulting structure to produce lateral insulating pieces from said third insulating layer on the sidewalls of said p-conducting layer and to expose the silicon substrate in the active zones of the MOS transistors and in the emitter and collector zones of the bipolar transistors, (p) applying a fourth insulating layer serving as a gate dielectric for the MOS transistors, (q) depositing a first undoped polysilicon layer over the full surface area, (r) structuring said first polysilicon layer and said fourth insulating layer with a photo-resist mask such that the substrate is exposed in the emitter and collector zones of the bipolar transistors, (s) removing the photo-resist mask of step (r), (t) depositing a second polysilicon layer over the resulting structure, (u) structuring said first and second polysilicon layers to form gate electrodes in said MOS transistors and emitter contacts in said bipolar transistors, (v) implanting phosphorus ions in the resulting structure to provide source/drain connection regions in the n-channel MOS transistors, (w) implanting arsenic ions in the resulting structures to produce source/drain zones in the n-channel transistors and doping the emitter and collector zones of the bipolar transistors, (x) implanting boron ions to produce source/drain zones in the p-channel transistors, (y) subjecting the resulting structure to a high temperature treatment on the order of 900° C. to diffuse arsenic into the source/drain zones of the n-channel transistors and into the emitter and collector zones, to diffuse boron into the source/drain zones of the p-channel transistors and into the base contact zones, and (z) forming electrical contacts to the p + - and n + -conducting terminals of the active transistor regions.