Carrier out-of-lock detector apparatus

Claim 2

Digital phase lock loop out-of-lock detector apparatus comprising, in combination: IEsgn first, IEnmsb second, QEsgn third, and QEnmsb fourth signal input means for supplying In-phase error sign and error NMSB (next most significant bit) and quadrature-phase error sign and error NMSB error signals respectively; exclusive OR fifth means, including input and output means, connected to said first and second means for receiving In-phase error signals and supplying a logic result at the output thereof; exclusive OR sixth means, including input and output means, connected to said third and fourth means for receiving quadrature-phase error signals and supplying a logic result at the output thereof; and integration type seventh means, including input and output means, connected to said fifth and sixth means, for supplying an out-of-lock apparatus output signal when both said fifth AND said sixth means provide an indication, for a majority of a given time, that one of their inputs have given logic values.

Claim 3

Apparatus as claimed in claim 1 wherein said given logic values are identical logic values.

Claim 6

Apparatus for detecting out-of-lock conditions in a QAM (quadrature amplitude modulated) digital phase-lock-loop (PLL) comprising, in combination: first means for providing In-phase and quadrature-phase sign and NMSB (next most significant bit) error bit signals; second means, connected to said first means, for exclusive-ORing the In-phase error sign and error NMSB (next most significant bit) error signals as detected to provide a first result signal; third means, connected to said first means, for exclusive-ORing the quadrature-phase error sign and error NMSB (next most significant bit) error signals as detected to provide a second result signal; detecting fourth means, for detecting the relative time that both said first AND second result signals are of a given identical logic value; and fifth means, comprising a part of said fourth means, for providing an output out-of-lock signal when either of the respective NMSB and error sign bits are of identical values for more than one-half the time.

Claim 7

Apparatus for detecting out-of-lock conditions in a QAM (quadrature amplitude modulated) digital phase-lock-loop (PLL) comprising, in combination: first means for providing In-phase and quadrature-phase sign and NMSB (next most significant bit) error bit signals; second means, connected to said first means, for exclusive-ORing the In-phase error sign and error NMSB (next most significant bit) error signals as detected to provide a first result signal; third means, connected to said first means, for exclusive-ORing the quadrature-phase error sign and error NMSB (next most significant bit) error signals as detected to provide a second result signal; detecting fourth means, for detecting the relative time that both said first AND second result signals are of a given identical logic value; and fifth means, comprising a part of said fourth means, for providing an output out-of-lock signal when either of the respective NMSB and error sign bits are of identical values for more than one-half the time.

Claim 8

Digital phase lock loop out-of-lock detector apparatus comprising, in combination: IEsgn first, IEnmsb second, QEsgn third, and QEnmsb fourth signal input means for supplying In-phase sign and NMSB (next most significant bit) and quadrature-phase sign and NMSB error signals respectively; logic fifth means, including input and first and second output means, connected to said first through fourth means for receiving said recited error signals therefrom and supplying an output signal indicative of whether or not either of the quadrature and In-phase signal pair are of identical logic conditions thereby indicating an error of at least a given amount; and logic sixth means, including input and output means and further including first and second counter means, connected to said fifth means for receiving output signals therefrom, actuating one or the other of said first and second counter means used as integrating means, for supplying an out-of-lock apparatus output signal when said fifth means provides an indication that at least one of the In and quadrature phase error signals supplied to said detector apparatus have identical logic values, for a majority of the time.

Claim 9

Digital phase lock loop out-of-lock detector apparatus comprising, in combination: IEsgn first, IEnmsb second, QEsgn third, and QEnmsb fourth signal input means for supplying In-phase sign and NMSB (next most significant bit) and quadrature-phase sign and NMSB error signals respectively; logic fifth means, including input and first and second output means, connected to said first through fourth means for receiving said recited error signals therefrom and supplying an output signal indicative of whether or not either of the quadrature and In-phase signal pair are of identical logic conditions thereby indicating an error of at least a given amount; and logic sixth means, including input and output means and further including first and second counter means, connected to said fifth means for receiving output signals therefrom, actuating one or the other of said first and second counter means used as integrating means, for supplying an out-of-lock apparatus output signal when said fifth means provides an indication that at least one of the In and quadrature phase error signals supplied to said detector apparatus have identical logic values, for a majority of the time.