← Back to Patent Explorer
US4534036A Expired / Lapsed US ⏱️ 0.0 years remaining

Phase tracking loop impairment monitor for modems

Assignee: Paradyne Corp
•
Filing: 1982-12-08
•
Granted: 1985-08-06
•
Expires: 2002-12-08
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract This invention provides a system which monitors the phase error signal generated by a phase tracking loop. The system includes a first circuit for averaging the phase error signal thus generating an uncorrected phase error, and a second signal for integrating the phase error to generate a corrected phase signal. The two generated signals are added together to yield a total phase error signal.

Inventors

  • 👤 William L. Betts
  • 👤 Kenneth Martinez

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-23 23:24
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 73 words
In a modem utilizing a phase tracking loop provided to correct phase error by generating an instantaneous phase error signal, a monitor system comprising: a first circuit for deriving a corrected phase error signal comprising an integrator which integrates said instantaneous error signal, a first absolute value generator means and a low pass filter means; and a second circuit for deriving an uncorrected phase error signal by averaging said instantaneous phase error signal.
Claim 2
Dependent Claim 73 words
In a modem utilizing a phase tracking loop provided to correct phase error by generating an instantaneous phase error signal, a monitor system comprising: a first circuit for deriving a corrected phase error signal comprising an integrator which integrates said instantaneous error signal, a first absolute value generator means and a low pass filter means; and a second circuit for deriving an uncorrected phase error signal by averaging said instantaneous phase error signal.
Claim 3
Dependent Claim 31 words
The monitor system of claim 1 wherein said second circuit comprises a second absolute value generator means and another low pass filter provided to average said output of said tracking loop.
Claim 4
Dependent Claim 31 words
The monitor system of claim 1, further comprising an adding means which adds said corrected phase error signal and said uncorrected phase error signal to generate a total phase error signal.
Claim 5
Dependent Claim 24 words
The monitor system of claim 1 wherein said first circuit further comprises means for eliminating the D.C. level of said output of said integrator.

References Cited (Backward Citations)

US4424497A Cited
US4442412A Cited
US4465982A Cited
US4456890A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1988-08-05 1989-02-04 1989-08-06 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1992-08-05 1993-02-04 1993-08-06 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1996-08-05 1997-02-04 1997-08-06 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag