Method and apparatus for calibrating an analog-to-digital conversion apparatus

Claim 1

A method of calibrating the phase relationship of N-phase clock signals (N: an integer larger than one) for an analog-to-digital conversion apparatus including clock generation means for generating the N-phase clock signals and N analog-to-digital converters for sampling a common analog input signal in response to the N-phase clock signals respectively and converting the sampled analog input signal into a digital signal, comprising the steps of: applying a repetitive analog reference signal to the N analog-to-digital converters in common, the analog reference signal being synchronized with the N-phase clock signals; selecting digital values provided by said N analog-to-digital converters at corresponding sampling points of different respective cycles of the reference signal; and, if the selected digital values are different from each other, adjusting the phase relationship of the N-phase clock signals in a manner such as to reduce the difference between the selected digital values from said N analog-to-digital converters.

Claim 2

A method of calibrating the phase relationship of N-phase clock signals (N: an integer larger than one) for an analog-to-digital conversion apparatus including clock generation means for generating the N-phase clock signals and N analog-to-digital converters for sampling a common analog input signal in response to the N-phase clock signals respectively and converting the sampled analog input signal into a digital signal, comprising the steps of: applying a repetitive analog reference signal to the N analog-to-digital converters in common, the analog reference signal being synchronized with the N-phase clock signals; selecting digital values provided by said N analog-to-digital converters at corresponding sampling points of different respective cycles of the reference signal; and, if the selected digital values are different from each other, adjusting the phase relationship of the N-phase clock signals in a manner such as to reduce the difference between the selected digital values from said N analog-to-digital converters.

Claim 9

An apparatus for calibrating the phase relationship of N-phase clock signals (N: an integer larger than one) for an analog-to-digital conversion apparatus including clock generation means for generating the N-phase clock signals and N analog-to-digital converters for sampling a common analog input signal in response to the N-phase clock signals respectively and converting the sampled analog input signal into a digital signal, comprising: reference signal generation means for generating a repetitive analog reference signal in synchronism with the clock signals and applying the reference signal to said N analog-to-digital converters in common; phase adjustment means for adjusting the phase relationship of the N-phase clock signals; and control means for selecting digital values provided by said N analog-to-digital converters at corresponding sampling points of different respective cycles of the reference signal and, if the selected digital values are different from each other, controlling said phase adjustment means in a manner such as to reduce the difference between the selected digital values from said N analog-to-digital converters.

Claim 10

An apparatus for calibrating the phase relationship of N-phase clock signals (N: an integer larger than one) for an analog-to-digital conversion apparatus including clock generation means for generating the N-phase clock signals and N analog-to-digital converters for sampling a common analog input signal in response to the N-phase clock signals respectively and converting the sampled analog input signal into a digital signal, comprising: reference signal generation means for generating a repetitive analog reference signal in synchronism with the clock signals and applying the reference signal to said N analog-to-digital converters in common; phase adjustment means for adjusting the phase relationship of the N-phase clock signals; and control means for selecting digital values provided by said N analog-to-digital converters at corresponding sampling points of different respective cycles of the reference signal and, if the selected digital values are different from each other, controlling said phase adjustment means in a manner such as to reduce the difference between the selected digital values from said N analog-to-digital converters.

Claim 19

A method of calibrating the phase relationship of N-phase clock signals (N: an integer larger than one), comprising the steps of: applying a repetitive analog reference signal to N analog-to-digital converters in common, the repetitive analog reference signal being synchronized with the N-phase clock signals; applying the N-phase clock signals to the N analog-to-digital converters respectively for sampling the analog reference signal and converting the sampled reference signal into a digital signal; selecting digital values provided by said N analog-to-digital converters at corresponding sampling points of different respective cycles of the repetitive reference signal; comparing the selected digital values with each other; and, if the selected digital values are not equal, adjusting the phase relationship of the N-phase clock signals in a manner such as to reduce the difference between the selected digital values.

Claim 20

A method of calibrating the phase relationship of N-phase clock signals (N: an integer larger than one), comprising the steps of: applying a repetitive analog reference signal to N analog-to-digital converters in common, the repetitive analog reference signal being synchronized with the N-phase clock signals; applying the N-phase clock signals to the N analog-to-digital converters respectively for sampling the analog reference signal and converting the sampled reference signal into a digital signal; selecting digital values provided by said N analog-to-digital converters at corresponding sampling points of different respective cycles of the repetitive reference signal; comparing the selected digital values with each other; and, if the selected digital values are not equal, adjusting the phase relationship of the N-phase clock signals in a manner such as to reduce the difference between the selected digital values.