Patent US4734749A successfully refreshed from Google Patents.
US4734749A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor mesa contact with low parasitic capacitance and resistance
Assignee: Skyworks Solutions Inc
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Filing: 1981-04-07
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Granted: 1988-03-29
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Expires: 2001-04-07
Abstract
Abstract Method of manufacturing silicon mesa diodes from a wafer of silicon. The surface of the wafer is coated with a first layer of silicon nitride and a second layer of silicon oxide. By masking and etching procedures, silicon nitride is left only on the portions of the surface defining the mesas to be formed. The wafer is etched to form the mesas and then treated to form a passivating silicon oxide coating at all the exposed surfaces of the wafer. The silicon nitride is removed from the upper surfaces of the mesas and metal contacts are applied to these upper surfaces. The wafer is subsequently divided into discrete dice, each containing a mesa, and the dice are mounted in suitable enclosures.
Inventors
- 👤 Clifford A. Levi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 17:04
CPC Classifications
H; H10; H10W; H10W74/00; H10W74/40; H10D; H10D99/00; H10P; H10P95/00
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
104 words
A mesa semiconductor device comprising, body of silicon semiconductor material having a top surface and edge surfaces defining a mesa of height within the range of 2-100 microns, the entire area of said edge surfaces being coated with a thermally grown passivating insulating silicon oxide layer, said top surface being entirely covered with a nitride, whereby said nitride may be removed by etching said device with phosphoric acid without removing said thermally grown passivating insulating silicon oxide layer so that said entire top surface may then receive a conducting layer establishing one of ohmic contact and a barrier junction with said entire top surface.
Claim 2
Dependent Claim
104 words
A mesa semiconductor device comprising, body of silicon semiconductor material having a top surface and edge surfaces defining a mesa of height within the range of 2-100 microns, the entire area of said edge surfaces being coated with a thermally grown passivating insulating silicon oxide layer, said top surface being entirely covered with a nitride, whereby said nitride may be removed by etching said device with phosphoric acid without removing said thermally grown passivating insulating silicon oxide layer so that said entire top surface may then receive a conducting layer establishing one of ohmic contact and a barrier junction with said entire top surface.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-03-29 | 1991-09-28 | 1992-03-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-03-29 | 1995-09-28 | 1996-03-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-03-29 | 1999-09-28 | 2000-03-29 | $7700.00 | Window Closed / Lapsed |