CML bias generator

Claim 1

A bias generator circuit for use with current-mode logic gates which has an output reference voltage that is substantially indepenent of supply potential and temperature variations, said generator circuit comprising: a first transistor having its collector connected to the supply potential via a first load resistor; a second transistor having its collector connected to the supply potential via a second load resistor and its base connected to the collector of said first transistor; said second transistor having its emitter coupled to an output node for generating an output reference voltage and connected to the base of said first transistor via an impedance compensating resistor; compensating means coupled to the emitter of said first transistor for minimizing variations in said output reference voltage as a function of changes in the supply potential and temperature; said compensating means being formed of a first emitter resistor and a diode-connected third transistor, said first emitter resistor having its one end connected to the emitter of said first transistor and to the collector and base of said third transistor, the emitter of said third transistor being connected to the other end of said first emitter resistor and to a ground potential; the value of the first emitter resistor controlling the output reference voltage for lower temperatures and the base-emitter voltage of the third transistor controlling the output reference voltage for higher temperatures; stabilizing means coupled to the emitter of said second transistor for maintaining the output reference voltage to be balanced; and said stabilizing means being formed of a fourth transistor and a second emitter resistor, said fourth transistor having its collector and base connected to the emitter of said second transistor and its emitter connected to one end of said second emitter resistor, the other end of said second emitter resistor being connected to the ground potential.