Interface circuit for data processing system

Claim 2

An interface circuit for a data processing apparatus comprising: a data input for receiving an input data signal; a digitizer circuit having an input and having an output, said input of said digitizer circuit being connected to said data input, for generating at its output a digital signal having a first logic state corresponding to said input data signal being at a voltage less than a first predetermined level, and having a second logic state corresponding to said input data signal being at a voltage greater than a second predetermined level; an output line conditioner circuit, comprising: a first switch means, connected between a first power supply node and an output node of said output line conditioner circuit, and connected to the output of said digitizer circuit, for connecting said first power supply node to said output node responsive to said digital signal being in its first logic state, and for isolating said first power supply node from said first power supply responsive to said digital signal being in its second logic state; and a second switch means, connected between a second power supply node and said output node, and connected to said data input for connecting said second power supply node to said output of said output line conditioner circuit responsive to said data input being at a voltage greater than said second predetermined level; and a line driver having an input connected to said output node of said output line conditioner for driving an output data line responsive to said voltage of said output node.

Claim 3

An interface circuit as claimed in claim 1, wherein: said digitizer circuit comprises an inverting Schmitt trigger circuit.

Claim 4

An interface circuit as claimed in claim 2, wherein said first switch means comprises: a first field effect device having its source-to-drain path connected between said first power supply node and said output node, and having its gate connected to said output of said digitizer circuit; and wherein said second switch means comprises: a second field effect device having its source-to-drain path connected between said output node and said second power supply node, and having a gate connected to said data input.

Claim 5

An interface circuit for a data processing apparatus comprising: a data input for receiving an input data signal; an inverting Schmitt trigger circuit having an input connected to said data input for generating at its output a digital signal at a first logic state responsive to said input data signal received by said data input being at a voltage below a first predetermined level, and at a second logic state responsive to said input data signal being at a voltage above a second predetermined level; an output line conditioner circuit including a first field effect device having its source-to-drain path connected between a first power supply node and a first output node, and having its gate connected to said output of said digitizer circuit so that said first field device connects said first power supply node to said first output node responsive to said digital signal being at its first logic state and so that said first output node is isolated from said first power supply node responsive to said digital signal being at its second logic state, and a second field effect device having its source-to-drain path connected between said first output node and a second power supply node, and having a gate connected to said data input so that said second field effect device connects said second power supply node to said first output node responsive to said data input being at a voltage greater than said second predetermined level, said output line conditioner circuit for generating an output signal on said first output node having a voltage level restricted between said the voltages of said first and second power supply nodes; and a line driver including a third field effect device having its source-to-drain path connected between said first power supply node and a second output node, and having its gate connected to receive a first clock signal, and a fourth field effect device having its source-to-drain path connected between said second output node and said first output node, and having its gate connected to receive a second clock signal, said first clock signal for precharging said second output node via said third field effect device, said second clock signal for discharging said second output node via said fourth field effect device dependent upon the voltage on said first output node, wherein said second output node is the output of said interface circuit.

Claim 6

An interface circuit for a data processing apparatus comprising: a data input for receiving an input data signal; an inverting Schmitt trigger circuit having an input connected to said data input for generating at its output a digital signal at a first logic state responsive to said input data signal received by said data input being at a voltage below a first predetermined level, and at a second logic state responsive to said input data signal being at a voltage above a second predetermined level; an output line conditioner circuit including a first field effect device having its source-to-drain path connected between a first power supply node and a first output node, and having its gate connected to said output of said digitizer circuit so that said first field device connects said first power supply node to said first output node responsive to said digital signal being at its first logic state and so that said first output node is isolated from said first power supply node responsive to said digital signal being at its second logic state, and a second field effect device having its source-to-drain path connected between said first output node and a second power supply node, and having a gate connected to said data input so that said second field effect device connects said second power supply node to said first output node responsive to said data input being at a voltage greater than said second predetermined level, said output line conditioner circuit for generating an output signal on said first output node having a voltage level restricted between said the voltages of said first and second power supply nodes; and a line driver including a third field effect device having its source-to-drain path connected between said first power supply node and a second output node, and having its gate connected to receive a first clock signal, and a fourth field effect device having its source-to-drain path connected between said second output node and said first output node, and having its gate connected to receive a second clock signal, said first clock signal for precharging said second output node via said third field effect device, said second clock signal for discharging said second output node via said fourth field effect device dependent upon the voltage on said first output node, wherein said second output node is the output of said interface circuit.

Claim 7

An interface circuit as claimed in claim 4, wherein: said first and second field effect devices of said output line conditioner circuit are constructed with their width-to-length ratios sized relative to one another so that the voltage of said first output node is pulled toward the voltage of said second power supply node responsive to said input data signal being at or above its second predetermined level, prior to said digital signal reaching its second logic state and causing said first field effect device to isolate said first output node from said first power supply node.

Claim 8

An interface circuit as claimed in claim 5, wherein: said first and second field effect devices of said output line conditioner circuit are constructed to match transistor-transistor logic signal levels to field effect transistor logic signal levels.