Fail memory equipment in memory tester

Claim 1

A fail memory equipment comprising: memory means having an equal number of memory blocks and input channels through which results of a memory test are inputted to said memory equipment; address input means temporarily storing addresses of memory test, for subsequently supplying an address to a corresponding memory block and selecting a memory cell of the corresponding memory block by decoding the address in response to a decode signal; test result input means selecting an input channel carrying the memory test result in response to a mode designation and temporarily storing the memory test result, for subsequently writing the memory test result into a corresponding memory block; serial/parallel control means responsive to the mode designation to produce the deocde signal from an address signal sent from said address input means; and clock control means responsive to a test clock and the mode designation to produce a storage instruction clock for the temporary storage of the address of memory test and the memory test result and a write clock for writing the memory test result into the memory block in accordance with an interleave mode, a serial mode or a parallel mode, whereby the memory test results obtained at a high speed from a memory being tested through input channels are written in parallel into the respective memory blocks under the interleave mode the memory test result obtained at a low speed from a large capacity memory being tested through an input channel are serially written into the respective memory blocks under the serial mode, and the memory test result obtained from a number of memories being tested simultaneously through input channels are written in parallel into the respective memory blocks under the parallel mode.