Patent US4733196A successfully refreshed from Google Patents.
US4733196A
Expired / Lapsed
US
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Current gain stage with low voltage drop
Assignee: STMicroelectronics SRL
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Filing: 1986-12-04
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Granted: 1988-03-22
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Expires: 2006-12-04
Abstract
Abstract A current gain stage with low voltage drop usable in place of a Darlington's current gain stage is described. This stage maintains the precision characteristics of the output current value, though presenting a lower voltage drop. The stage is formed by connecting the collector of the input transistor (driver) to a current mirror, the output current of which is added to the output current of the gain stage for maintaining the high precision.
Inventors
- 👤 Pietro Menniti
- 👤 Antonella Lanati
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 20:50
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/34; H03F3/343; H03F3/3432; H03F3/3435
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
135 words
A current gain stage having an input terminal and an output terminal and operable to produce an output current which is a precise amplified replica of a current applied to said input terminal, said current gain stage comprising: a first transistor and a second transistor substantially connected in cascade, each of said transistors having a load connected to its collector, the base of said first transistor constituting said input terminal and the collector of said second transistor constituting said output terminal, each of said transistors having respective collector currents; wherein the collector load of said first transistor is a current mirror operable to produce an output current equal to the collector current of said first transistor; and wherein the output current of said current mirror is added to the collector current of said second transistor.
Claim 2
Dependent Claim
135 words
A current gain stage having an input terminal and an output terminal and operable to produce an output current which is a precise amplified replica of a current applied to said input terminal, said current gain stage comprising: a first transistor and a second transistor substantially connected in cascade, each of said transistors having a load connected to its collector, the base of said first transistor constituting said input terminal and the collector of said second transistor constituting said output terminal, each of said transistors having respective collector currents; wherein the collector load of said first transistor is a current mirror operable to produce an output current equal to the collector current of said first transistor; and wherein the output current of said current mirror is added to the collector current of said second transistor.
Claim 3
Dependent Claim
58 words
The current gain stage of claim 1, further comprising: a second current mirror driven by the collector current of said second transistor and operable to produce an output current equal to the collector current of said second transistor; and wherein the output current of said current mirror is added to the output current of said second current mirror.
Claim 4
Dependent Claim
59 words
The current gain stage of claim 1, further comprising: a second current mirror driven by the output current of said current mirror driven by the collector current of said first transistor; and wherein the output current of said second current mirror is added directly to the current passing through the load connected to the collector of said second transistor.
References Cited (Backward Citations)
US4420725A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-03-22 | 1991-09-21 | 1992-03-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-03-22 | 1995-09-21 | 1996-03-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-03-22 | 1999-09-21 | 2000-03-22 | $7700.00 | Window Closed / Lapsed |