Low current high precision CMOS schmitt trigger circuit

Claim 2

A Schmitt Trigger circuit comprising: a differential comparator having a first input for receiving an input signal, a second input for receiving a comparison signal to be compared to the input signal, an output switchable from a first output state to a second output state, and power supply terminals for the application of current from a power supply to the comparator; feedback means, coupled to the second input, for providing one of a predetermined first and second voltages as the comparison signal in accordance with the output state of the comparator, said feedback means including power supply terminals for the application of current from the power supply to the feedback means; and switch means, coupled to at least one of the power supply terminals of the comparator and feedback means and controlled by the input signal, for controlling the application of current from the power supply to at least one of the comparator and feedback means.

Claim 3

A circuit as in claim 1 wherein the input voltage controls the application of current to both the comparator and the feedback means.

Claim 4

A circuit as in claim 1 wherein the comparator includes first and second supply terminals and the switch means includes a first MOS transitor of first conductivity type having its gate connected to receive the input signal, its source disposed for connection to a first power supply and its drain operatively coupled to the first supply terminal, and a second transistor of second conductivity type having its gate connected to receive the input signal, its source disposed for connection to a second power supply and its drain operatively coupled to the second supply terminal.

Claim 5

A circuit as in claim 2 wherein the comparator includes first and second supply terminals, the feedback means includes third and fourth supply terminals and the switch means includes a first transistor of first conductivity type having its gate connected to receive the input signal, its source disposed for connection to a first power supply and its drain operatively coupled to the first supply terminal, a second transistor of second conductivity type having its gate connected to receive the input signal, its source disposed for connection to a second power supply and its drain operatively coupled to the second supply terminal, a third transistor of first conductivity type having its gate connected to receive the input signal, its source disposed for connection to the first power supply and its drain operatively coupled to the third supply terminal, and a fourth transistor of second conductivity type having its gate connected to receive the input signal, its source disposed for connection to the second power supply and its drain operatively coupled to the fourth supply terminal.

Claim 6

A circuit as in claim 4 wherein the comparator includes a pair of MOS transistors of the same conductivity type having their sources interconnected and connected to receive current from the first supply terminal, wherein the gate of one transistor is the first input and the gate of the other transistor is the second input, wherein the drain of one of the transistors is the output of the comparator.

Claim 7

A circuit as in claim 5 including an inverter having an input connected to the output of the comparator, wherein the feedback means includes a switchable voltage divider driven by the output of the inverter, wherein when the output of the inverter is at a high level the voltage divider provides the first voltage and when the output of the inverter is at a low level the voltage divider provides the second voltage.

Claim 8

A circuit as in claim 6 wherein the voltage divider includes a control transistor driven by the output of the inverter, first and second voltage dividing elements connected in series between the drains of the third and fourth transistors, the connection point of the voltage dividing elements being the output of the feedback means, a third voltage dividing element connected in series with the control transistor, wherein the third voltage dividing element and control transistor are connected in parallel with the second voltage dividing element, wherein the control transistor is rendered conductive or non-conductive by the output of the inverter to determine the value of the output of the feedback means.

Claim 9

A circuit as in claim 7 wherein the voltage dividing elements are resistors.

Claim 10

A circuit as in claim 7 wherein the voltage dividing elements are diode connected MOS transistors.

Claim 11

A Schmitt Trigger circuit comprising: a differential section including first and second MOS transistors having their sources interconnected and an output at the drain of one of the transistors, an input terminal connected to the gate of the first transistor for receiving an input signal, and a feedback terminal connected to the gate of the second transistor for receiving a feedback signal, wherein the output will be a first level when the input signal is greater than the feedback signal and a second level when the input signal is less than the feedback signal; a feedback section, coupled to the feedback terminal and controlled by the output of the differential section, for providing one of a predetermined first and second signals as the feedback signal; a power supply terminal for supplying power to at least one of the differential section and feedback section; and CMOS switch means, connected to the power supply terminal and controlled by the input signal, for controlling the application of power to at least one of the differential section and the feedback section.

Claim 12

A Schmitt Trigger circuit comprising: a differential section including first and second MOS transistors having their sources interconnected and an output at the drain of one of the transistors, an input terminal connected to the gate of the first transistor for receiving an input signal, and a feedback terminal connected to the gate of the second transistor for receiving a feedback signal, wherein the output will be a first level when the input signal is greater than the feedback signal and a second level when the input signal is less than the feedback signal; a feedback section, coupled to the feedback terminal and controlled by the output of the differential section, for providing one of a predetermined first and second signals as the feedback signal; a power supply terminal for supplying power to at least one of the differential section and feedback section; and CMOS switch means, connected to the power supply terminal and controlled by the input signal, for controlling the application of power to at least one of the differential section and the feedback section.

Claim 13

A circuit as in claim 10 wherein the switch means includes: a third transistor of first conductivity type having its gate connected to receive the input signal, its source disposed for connection to a first power supply and its drain connected to supply current to the interconnected sources of the first and second transistors; and a fourth transistor of second conductivity type having its gate connected to receive the input signal, its source disposed for connection to a second power supply and its drain operatively coupled to the drain of at least one of the first and second transistors, wherein the third and fourth transistors are both rendered conductive within a voltage range of the input signal that includes the first and second feedback signals.

Claim 14

A circuit as in claim 11 including a CMOS inverter having an input connected to the output of the differential section, wherein the output of the inverter controls the feedback section.

Claim 15

A circuit as in claim 11 wherein the feedback section includes a switchable voltage divider for providing one of the first and second feedback signals at the feedback terminal.

Claim 16

A circuit as in claim 13 wherein the feedback section includes a pair of power supply terminals, connected to the switch means, through which power is supplied to the feedback section.

Claim 17

A circuit as in claim 14 wherein the voltage divider includes: first and second voltage dividing elements connected in series between the feedback section power supply terminals, wherein the point between the voltage dividing elements is connected to the feedback terminal; a third voltage dividing element; and a MOS transistor switch controlled by the output of the differential section and connected in series with the third voltage dividing element, wherein the transistor switch and third voltage dividing element are connected in parallel with the second voltage dividing element.

Claim 18

A circuit as in claim 15 wherein the voltage dividing elements are resistors.

Claim 19

A circuit as in claim 15 wherein the voltage dividing elements are diode connected transistors.

Claim 20

A circuit as in claim 11 wherein the differential section includes a current source MOS transistor, driven by a bias voltage, having one of its drain and source connected to the drain of the third transistor and the other of its drain and source connected to the interconnected sources of the first and second transistors.

Claim 21

A circuit as in claim 18 wherein the feedback section includes first and second power supply terminals through which power is supplied to the feedback section, and wherein the third transistor is operatively coupled to the first power supply terminal, the switch means further including a fifth transistor of second conductivity type having its gate connected to receive the input signal, its source disposed for connection to the second power supply and its drain connected to the second supply terminal of the feedback means.

Claim 22

A circuit as in claim 18 wherein the feedback section includes first and second power supply terminals through which power is supplied to the feedback circuit, wherein the switch means further includes: a fifth transistor of first conductivity type having its gate connected to receive the input signal, its source disposed for connection to the first power supply and its drain operatively coupled to the first power supply terminal; and a sixth transistor having its gate connected to receive the input signal, its source disposed for connection to the second power supply and its drain operatively coupled to the second power supply terminal.

Claim 23

A circuit as in claim 20 further including a seventh MOS transistor having one of its source and drain connected to the drain of the fifth transistor, the other of the source and drain connected to the first power supply terminal, and its gate connected to receive a reference voltage, said seventh transistor providing a precise current to the feedback means.

Claim 24

A circuit as in claim 11 further including a resistor connected between the drains of the second transistors.

Claim 25

A circuit as in claim 11 further including a pair of current mirror connected MOS transistors, the drain of one of the transistors connected to the drain of the first transistor and the drain of the other of the transistors connected to the drain of the second transistor, the sources of the current mirror transistors being connected to the drain of the fourth transistor.

Claim 26

A CMOS Schmitt Trigger circuit comprising: power supply means for supplying power to the circuit, said power supply means having first and second power supply terminals; a differential comparator section, coupled to receive power from the first power supply terminal, including first and second MOS transistors having their sources interconnected and an output at the drain of one of the transistors, an input terminal connected to the gate of the first transistor for receiving an input signal, and a feedback terminal connected to the gate of the second transistor for receiving a feedback signal, wherein the output will be a first level when the input signal is greater than the feedback signal and a second level when the input signal is less than the feedback signal; a feedback section, coupled to receive power from the second power supply terminal and to be controlled by the output of the differential section, for providing to the feedback terminal one of a predetermined first and second feedback voltages as the feedback signal; and CMOS switch means, including at least a third MOS transistor connected to the first power supply terminal and controlled by the input signal and a fourth MOS transistor connected to the second power supply terminal and controlled by the input signal, for controlling the application of power to the differential section and the feedback section, said third and fourth transistors being rendered simultaneously conductive for a range of input signal values that includes the first and second feedback volages.

Claim 27

A CMOS Schmitt Trigger circuit comprising: power supply means for supplying power to the circuit, said power supply means having first and second power supply terminals; a differential comparator section, coupled to receive power from the first power supply terminal, including first and second MOS transistors having their sources interconnected and an output at the drain of one of the transistors, an input terminal connected to the gate of the first transistor for receiving an input signal, and a feedback terminal connected to the gate of the second transistor for receiving a feedback signal, wherein the output will be a first level when the input signal is greater than the feedback signal and a second level when the input signal is less than the feedback signal; a feedback section, coupled to receive power from the second power supply terminal and to be controlled by the output of the differential section, for providing to the feedback terminal one of a predetermined first and second feedback voltages as the feedback signal; and CMOS switch means, including at least a third MOS transistor connected to the first power supply terminal and controlled by the input signal and a fourth MOS transistor connected to the second power supply terminal and controlled by the input signal, for controlling the application of power to the differential section and the feedback section, said third and fourth transistors being rendered simultaneously conductive for a range of input signal values that includes the first and second feedback volages.