US4733077A
Expired / Lapsed
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Noise immune infrared readout circuitry
Assignee: Raytheon Co
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Filing: 1984-12-20
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Granted: 1988-03-22
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Expires: 2004-12-20
Abstract
Abstract A new technique, and output encoding circuits using that technique, are disclosed for interfacing between a semiconductor IR detector 23 and associated output electronics 24, 25, 26 which technique and circuits transfer a charge packet onto a sense capacitor 22 that previously stored a reset level signal. The resulting stepped signal change, or delta, in the voltage present on that capacitor 22 is employed as the output signal.
Inventors
- 👤 Steve D. Gaalema
- 👤 Mary J. Hewitt
- 👤 Arthur L. Morse
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 04:49
CPC Classifications
H; H04; H04N; H04N25/00; H04N25/60; H04N25/616; H04N25/70; H04N25/76; H04N25/77; H04N25/771; H04N25/65
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
158 words
An output encoding circuit for an associated IR detector element, the circuit including: (1) a first capacitive element; (2) means to periodically impose a signal across the first capacitive element proportional to the reset level of an associated infrared detector, so as to initiate a frame interval; (3) means to accumulate the output of the associated infrared detector for a frame interval; and (4) means (a) to readout from the first capacitive element the reset signal level, then (b) to impose on the first capacitive element a signal proportional to the output of the IR detector, and then (c) to readout the IR detector signal on the first capacitive element, these sequential operations (a), (b) and (c) defining a pixel address period substantially less than the frame interval, such that output encoding circuit produces a stepped output voltage representative of the delta change on the first capacitive element during the sequential readout operations for each successive frame interval.
Claim 2
Dependent Claim
158 words
An output encoding circuit for an associated IR detector element, the circuit including: (1) a first capacitive element; (2) means to periodically impose a signal across the first capacitive element proportional to the reset level of an associated infrared detector, so as to initiate a frame interval; (3) means to accumulate the output of the associated infrared detector for a frame interval; and (4) means (a) to readout from the first capacitive element the reset signal level, then (b) to impose on the first capacitive element a signal proportional to the output of the IR detector, and then (c) to readout the IR detector signal on the first capacitive element, these sequential operations (a), (b) and (c) defining a pixel address period substantially less than the frame interval, such that output encoding circuit produces a stepped output voltage representative of the delta change on the first capacitive element during the sequential readout operations for each successive frame interval.
Claim 3
Dependent Claim
44 words
An output encoding circuit as set forth in claim 1 in which said means to accumulate the detector's output includes a second capacitive element, the readout means including a transfer gate FET for selectively connecting the second capacitive element to the first capacitive element.
Claim 4
Dependent Claim
66 words
An output encoding circuit as set forth in claim 2 in which the means to impose the reset signal comprises a reset gate FET, the input to which may connected to a reference voltage source and the output of which is directly connected to said first capacitive element, and further including a transfer gate FET to selectively impose the reset signal on said second capacitive element.
Claim 5
Dependent Claim
43 words
An output encoding circuit as set forth in claim 3, further including a buffer FET connected between the detector and said second capacitive element for maintaining a constant detector bias and permitting direct injection of the detector signal onto said second capacitive element.
Claim 6
Dependent Claim
32 words
An output encoding circuit as set forth in claim 2 in which the means to readout the IR detector signal on the second capacitive element reads out substantially all of said signal.
Claim 7
Dependent Claim
21 words
An output encoding circuit as set forth in claim 2 in which the second capacitive element is a FET storage well.
Claim 8
Dependent Claim
38 words
An output encoding circuit as set forth in claim 6 in which said the detector and the associated output encoding circuit are located physically adjacent to one another on a semiconductor's surface and as part of an array.
Claim 9
Dependent Claim
23 words
An output encoding circuit as set forth in claim 6 in which the FET storage well is part of a Tompsett sampler circuit.
Claim 10
Dependent Claim
43 words
An output encoding circuit as set forth in claim 8 in which said second capacitive element is connected to the diffusion layer of the FET storage well, and including means to selectively electrically isolate the second capacitive element from the first capacitive element.
Claim 11
Dependent Claim
37 words
An output encoding circuit as set forth in claim 1 in which said the detector and the associated output encoding circuit are located physically adjacent one another on a semiconductor's surface and as part of an array.
Claim 12
Dependent Claim
26 words
An output encoding circuit as set forth in claim 6, including a synthetic transimpedance amplifier connected to supply the detector signal to the FET storage well.
Claim 13
Dependent Claim
50 words
An output encoding circuit as set forth in claim 2 in which the second capacitive element is connected in series to supply the detector signal to said transfer gate FET, and further including a clamp gate FET connected to selectively return said first capacitive element to a reset signal condition.
Claim 14
Dependent Claim
45 words
An output encoding circuit as set forth in claim 12 in which the clamp gate FET is connected between said second capacitive element and said transfer gate FET to, with the transfer gate FET, selectively return said first capacitive element to a reset signal condition.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-03-22 | 1991-09-21 | 1992-03-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-03-22 | 1995-09-21 | 1996-03-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-03-22 | 1999-09-21 | 2000-03-22 | $7700.00 | Window Closed / Lapsed |