Autoranging time stamp circuit

Claim 2

A circuit for associating time values with specified events stored in a memory, comprising: means for generating a plurality of different known clock frequencies; means for selecting in order of decreasing frequency the clock frequencies to provide a clock signal; means for generating in response to the clock signal a binary code count to be associated as a time value with each specified event to be stored; means for signaling the occurrence of a specified event; and control means responsive to the signaling means to reset the clock frequency to its initial frequency in the predetermined order each time a specified event occurs.

Claim 3

The circuit of claim 1 in which a portion of the binary code count is fed back to the frequency selecting means to select the clock frequencies in the predetermined order.

Claim 4

The circuit of claim 2 in which the control means resets the binary code count in response to the signaling of a specified event, the portion of the reset count fed back to the frequency selecting means thereby selecting the initial frequency.

Claim 5

The circuit of claim 1 including means for comparing the binary code counts associated with at least two specified events to determine the time elapsed between the events.

Claim 6

The circuit of claim 1 in which the clock frequency generating means includes an oscillator providing a clock signal of a predetermined clock frequency to a plurality of counters connected in cascade, the counters dividing the predetermined frequency to generate the plurality of clock frequencies.

Claim 7

A circuit for associating time values with specified events stored in a memory, comprising: means for generating a plurality of different known clock frequencies; a multiplexer for selecting in order of decreasing frequency the clock frequencies to provide a clock signal; means for generating in response to the clock signal a binary code count to be associated as a time value with each specified event to be stored; means for signaling the occurrence of a specified event; and control means responsive to the signaling means to reset the clock frequency to its initial frequency in the predetermined order each time a specified event occurs.

Claim 8

A circuit for associating time values with specified events stored in a memory, comprising: means for generating a plurality of different known clock frequencies; a multiplexer for selecting in order of decreasing frequency the clock frequencies to provide a clock signal; means for generating in response to the clock signal a binary code count to be associated as a time value with each specified event to be stored; means for signaling the occurrence of a specified event; and control means responsive to the signaling means to reset the clock frequency to its initial frequency in the predetermined order each time a specified event occurs.

Claim 9

The circuit of claim 1 in which the binary code is a reflected code.

Claim 10

The circuit of claim 1 in which the clock frequencies range from one hertz to five megahertz.

Claim 11

The circuit of claim 1 in which the binary code generating means comprises a plurality of programmable logic arrays and the control means comprises a programmable logic array, the control programmable logic array enabling the counter programmable logic arrays to count simultaneously in generating the binary code count.

Claim 12

The circuit of claim 1 including means for warning that two specified events have occurred too close in time to generate binary code counts that validly reflect the time therebetween.

Claim 13

In a data acquisition system that stores specified events in memory, a circuit for associating a time value with each specified event that is stored for measuring the time between the events, the circuit comprising: an oscillator providing a clock frequency; a plurality of counters clocked by the oscillator and connected in cascade to divide the oscillator frequency, each counter generating a clock signal of predetermined frequency, the frequencies having a decreasing order; a plurality of counter programmable logic arrays for generating a Gray code count, the count generated in response to a clock signal provided by one of the predetermined frequencies; a multiplexer for selecting in response to a portion of the Gray code count the clock frequencies in the decreasing order to provide the clock signal to the counter programmable logic arrays; and a control programmable logic array for sensing the occurrence of a specified event and in response resetting the Gray code count to an initial count and through the reset of the count resetting the clock frequency to its initial frequency in the predetermined order.

Claim 14

In a data acquisition system that stores specified events in memory, a circuit for associating a time value with each specified event that is stored for measuring the time between the events, the circuit comprising: an oscillator providing a clock frequency; a plurality of counters clocked by the oscillator and connected in cascade to divide the oscillator frequency, each counter generating a clock signal of predetermined frequency, the frequencies having a decreasing order; a plurality of counter programmable logic arrays for generating a Gray code count, the count generated in response to a clock signal provided by one of the predetermined frequencies; a multiplexer for selecting in response to a portion of the Gray code count the clock frequencies in the decreasing order to provide the clock signal to the counter programmable logic arrays; and a control programmable logic array for sensing the occurrence of a specified event and in response resetting the Gray code count to an initial count and through the reset of the count resetting the clock frequency to its initial frequency in the predetermined order.

Claim 17

The method of claim 12 including reading the binary code count to select the clock frequency providing the clock signal and resetting the binary code count each time a specified event occurs to reset the clock frequency.

Claim 18

The method of claim 12 including warning that two specified events have occurred too close in time to generate binary output counts that validly reflect the time therebetween.

Claim 19

The method of claim 12 including comparing the binary code count of two events to determine the elapsed time between the events.