Integrated circuit comprising MOS transistors having electrodes of metallic silicide and a method of fabrication of said circuit

Claim 1

A method of fabrication of an integrated circuit, wherein said method comprises the following successive steps: (a) formation of an insulating thin film constituting the gate insulator of a field-effect transistor on a substrate of monocrystalline silicon of a first conductivity type in an active zone of said substrate; (b) etching of the insulating layer with a view to baring the monocrystalline silicon in source and drain electrical contact zones between source and drain regions and corresponding electrodes; (c) uniform deposition of a metallic silicide over the entire substrate so that the silicide rests on the gate insulatr at locations in which said insulator is present and comes into direct contact with the monocrystalline silicon on the remainder of the active zone; (d) deposition of a photosensitive layer which is capable of affording resistance to the silicide etching products and of serving as a mask for stopping impurities at the time of an operation involving implantation of impurities; (e) photoetching of the photosensitive layer in order to form a resin pattern comprising a portion of resin above the gate insulator, said portion being intended to correspond to the pattern of the gate to be formed, and portions of resin defining a source electrode, a drain electrode and interconnections, the resin being removed along the edges of the gate above the active zone and permitted to remain above the silicide in portions of active zone in which the silicon; (f) removal of the silicide by etching at locations in which it is not protected by the resin; (g) ion implantation of impurities in order to define source and drain regions; (h) removal of the resin; (i) annealing of the substrate.

Claim 2

A method of fabrication of an integrated circuit, wherein said method comprises the following successive steps: (a) formation of an insulating thin film constituting the gate insulator of a field-effect transistor on a substrate of monocrystalline silicon of a first conductivity type in an active zone of said substrate; (b) etching of the insulating layer with a view to baring the monocrystalline silicon in source and drain electrical contact zones between source and drain regions and corresponding electrodes; (c) uniform deposition of a metallic silicide over the entire substrate so that the silicide rests on the gate insulatr at locations in which said insulator is present and comes into direct contact with the monocrystalline silicon on the remainder of the active zone; (d) deposition of a photosensitive layer which is capable of affording resistance to the silicide etching products and of serving as a mask for stopping impurities at the time of an operation involving implantation of impurities; (e) photoetching of the photosensitive layer in order to form a resin pattern comprising a portion of resin above the gate insulator, said portion being intended to correspond to the pattern of the gate to be formed, and portions of resin defining a source electrode, a drain electrode and interconnections, the resin being removed along the edges of the gate above the active zone and permitted to remain above the silicide in portions of active zone in which the silicon; (f) removal of the silicide by etching at locations in which it is not protected by the resin; (g) ion implantation of impurities in order to define source and drain regions; (h) removal of the resin; (i) annealing of the substrate.