Patent US4730208A successfully refreshed from Google Patents.
US4730208A
Expired / Lapsed
US
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Semiconductor device
Assignee: TOKYO SAHBAURA DENKI 72 HORIKAWA-CHO SAIWAI-KU KAWASAKI-SHI KANAGAWA-KEN JAPAN KK
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Filing: 1986-11-21
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Granted: 1988-03-08
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Expires: 2006-11-21
Abstract
Abstract A semiconductor device including an input circuit, in which an impurity region is formed in a semiconductor substrate under the input circuit. This impurity region has a conductivity type opposite to that of the substrate or at least has a lower impurity concentration than that of the substrate. According to this structure, the input voltage capability of the device is improved. Additionally, the fabrication methods of this semiconductor device are disclosed.
Inventors
- 👤 Eitaro Sugino
- 👤 Akira Morikuri
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 16:39
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/40; H10D1/47; H10D89/00; H10D89/60; H10D89/601; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/012; H10W10/0125; H10W10/0126; H10W10/0127; H10W10/10; H10W10/13; H10W72/00; H10W72/01; H10W72/019; H10W70/00; H10W70/60; H10W72/90; H10W72/921; H10W72/923; H10W72/951; H10W72/952; H10W72/981; H10W72/983
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
239 words
A semiconductor device with MOS FET circuits, comprising: a semiconductor substrate having one conductivity type; an insulation layer formed on said substrate; an active portion formed in said substrate and coupled to the MOS FET circuits; an input protection resistor, having one end coupled to said active portion, formed on said insulation layer; a bonding pad, connected to another end of said input protection resistor, formed on said insulation layer; an impurity diffusion region having an opposite conductivity type relative to said one conductivity type formed underlying said insulation layer, said impurity diffusion region positioned at least under said input protection resistor and electrically maintained at floating potential level; and a channel stopper region having said one conductivity type and a higher impurity concentration than that of said substrate, formed underlying said insulation layer, said channel stopper region positioned at the surface portion of said semiconductor substrate except for the portion where said impurity diffusion region is formed; wherein said insulation layer overlying said impurity diffusion region is not thicker than that of said insulation layer overlying said channel stopper region and when a voltage of a predetermined polarity is applied across the bonding pad, the insulating layer and the substrate, a depletion layer is formed between said impurity diffusion region and the substrate such that the applied voltage is divided by the insulating layer and the depletion layer thereby to reduce the voltage existing across the insulating layer.
Claim 2
Dependent Claim
239 words
A semiconductor device with MOS FET circuits, comprising: a semiconductor substrate having one conductivity type; an insulation layer formed on said substrate; an active portion formed in said substrate and coupled to the MOS FET circuits; an input protection resistor, having one end coupled to said active portion, formed on said insulation layer; a bonding pad, connected to another end of said input protection resistor, formed on said insulation layer; an impurity diffusion region having an opposite conductivity type relative to said one conductivity type formed underlying said insulation layer, said impurity diffusion region positioned at least under said input protection resistor and electrically maintained at floating potential level; and a channel stopper region having said one conductivity type and a higher impurity concentration than that of said substrate, formed underlying said insulation layer, said channel stopper region positioned at the surface portion of said semiconductor substrate except for the portion where said impurity diffusion region is formed; wherein said insulation layer overlying said impurity diffusion region is not thicker than that of said insulation layer overlying said channel stopper region and when a voltage of a predetermined polarity is applied across the bonding pad, the insulating layer and the substrate, a depletion layer is formed between said impurity diffusion region and the substrate such that the applied voltage is divided by the insulating layer and the depletion layer thereby to reduce the voltage existing across the insulating layer.
Claim 3
Dependent Claim
16 words
A semiconductor device as recited in claim 1, wherein said resistor comprises: a polycrystalline silicon layer.
Claim 4
Dependent Claim
21 words
A semiconductor device as recited in claim 1, comprising: said impurity diffusion region formed under said resistor and said bonding pad.
Claim 5
Dependent Claim
41 words
A semiconductor device as recited in claim 1 comprising: said resistor connected to said bonding pad by a conductive layer formed on said insulation layer; and said impurity diffusion region formed under said bonding pad, said conductive layer and said resistor.
Claim 6
Dependent Claim
71 words
A semiconductor device as recited in claim 1, comprising: a well region having a conductivity type opposite that of said substrate formed in said substrate, said active portion being formed in said well region; and a second impurity region having said opposite conductivity type, formed in a surface area of said well region except for said active portion, said second impurity region and said impurity diffusion region having been simultaneously formed.
Claim 7
Dependent Claim
71 words
A semiconductor device as recited in claim 2, comprising: a well region having a conductivity type opposite that of said substrate formed in said substrate, said active portion being formed in said well region; and a second impurity region having said opposite conductivity type, formed in a surface area of said well region except for said active portion, said second impurity region and said impurity diffusion region having been simultaneously formed.
Claim 8
Dependent Claim
46 words
A semiconductor device as recited in claim 1, comprising: a well region, having a conductivity type opposite that of said substrate, formed in said substrate, said active portion being formed in said well region, said well region and said impurity diffusion region having been simultaneously formed.
Claim 9
Dependent Claim
46 words
A semiconductor device as recited in claim 2, comprising: a well region, having a conductivity type opposite that of said substrate, formed in said substrate, said active portion being formed in said well region, said well region and said impurity diffusion region having been simultaneously formed.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-03-08 | 1991-09-07 | 1992-03-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-03-08 | 1995-09-07 | 1996-03-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-03-08 | 1999-09-07 | 2000-03-08 | $7700.00 | Window Closed / Lapsed |