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US4730157A
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Circuit for the real time analysis of the energy distribution of pulses of a pulse signal
Assignee: Commissariat à l'Énergie Atomique et Aux Énergies Alternatives
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Filing: 1986-03-12
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Granted: 1988-03-08
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Expires: 2006-03-12
Abstract
Abstract It comprises an analog-digital converter receiving the pulse signal and supplying, for each pulse, a first code representing the amplitude of said pulse, said first code being able to assume N values, a group of n scalers, in which n<N, each corresponding to an energy window and a coding means receiving said first code and supplying a second code for addressing one of the counting scales, whereby said second code can assume at least n values, the content of the addressed scaler being incremented, said coding means comprising a memory and a binary decoder, the memory having N storage cells and receiving the first code on its address input, the binary decoder being connected by its input to the data output of the memory and supplying the second code.
Inventors
- 👤 Jean L. Lepetit
- 👤 Jean P. Lepagnot
- 👤 Emile Poussier
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 15:31
CPC Classifications
G; G01; G01R; G01R19/00; G01R19/165; G01R19/17
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
184 words
A circuit for the real time analysis of the amplitude of the pulses of a pulse signal, said analysis comprising counting the pulses appearing in each of a plurality of windows of energy, said circuit comprising: an analog-digital converter means receiving said pulse signal and supplying for each pulse a digital signal which is a function of the amplitude of said pulse, a memory means having locations, said memory means being addressed by said digital signal, each location containing a code indicating the window of energy corresponding to the amplitude of the pulse signal which corresponds to said location, said memory means supplying the code memorized in the location addressed by said digital signal, a decoder means having an input and a plurality of outputs, said decoder means receiving on said input said code from said memory means and supplying a signal on one of said outputs as a function of said code, a plurality of counting means, each counting means being connected to one output of said decoder means, and having means for storing the number of signals received from said decoder means.
Claim 2
Dependent Claim
184 words
A circuit for the real time analysis of the amplitude of the pulses of a pulse signal, said analysis comprising counting the pulses appearing in each of a plurality of windows of energy, said circuit comprising: an analog-digital converter means receiving said pulse signal and supplying for each pulse a digital signal which is a function of the amplitude of said pulse, a memory means having locations, said memory means being addressed by said digital signal, each location containing a code indicating the window of energy corresponding to the amplitude of the pulse signal which corresponds to said location, said memory means supplying the code memorized in the location addressed by said digital signal, a decoder means having an input and a plurality of outputs, said decoder means receiving on said input said code from said memory means and supplying a signal on one of said outputs as a function of said code, a plurality of counting means, each counting means being connected to one output of said decoder means, and having means for storing the number of signals received from said decoder means.
Claim 3
Dependent Claim
68 words
A circuit according to claim 1, wherein the amplitude of the pulses are comprised in a predetermined range of amplitudes, and the windows of energy correspond to various portions of the range, said circuit having counting means for counting the pulses in each of the respective windows of energy and a supplementary counting means for counting the pulses which amplitude is not included in said windows of energy.
Claim 4
Dependent Claim
13 words
A circuit according to claim 1, wherein the memory means is a RAM.
Claim 5
Dependent Claim
15 words
A circuit according to claim 1, wherein the memory means is an EPROM or EEPROM.
References Cited (Backward Citations)
US2806651A
Cited
US2961641A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-03-08 | 1991-09-07 | 1992-03-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-03-08 | 1995-09-07 | 1996-03-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-03-08 | 1999-09-07 | 2000-03-08 | $7700.00 | Window Closed / Lapsed |