Abstract An inverter having an output connected to a load through a reactor and an output filter capacitor terminal voltage of the capacitor is monitored, and an interlock operation for interrupting the delivery of the inverter transistor drive signals is released when the terminal voltage does not exceed a predetermined level. When the interlock operation for cutting off the drive signals of the transistors has started and continued for a predetermined time, it is further continued when the terminal voltage of the output filter capacitor does not drop below a set level and is released for the first time when the output filter capacitor is sufficiently discharged to render the terminal voltage the set level or below.
In an inverter apparatus wherein an output of an inverter is fed to a load through a reactor and a capacitor for shaping a waveform, and wherein a control circuit which supplies the inverter with drive signals includes means to detect an overload of the inverter and to perform an interlock operation for interrupting delivery of the drive signals during the overload; an inverter apparatus characterized by monitoring a terminal voltage of said capacitor, and releasing the interlock operation on condition that the terminal voltage does not exceed a predetermined level.
Claim 2
Dependent Claim
91 words
In an inverter apparatus wherein an output of an inverter is fed to a load through a reactor and a capacitor for shaping a waveform, and wherein a control circuit which supplies the inverter with drive signals includes means to detect an overload of the inverter and to perform an interlock operation for interrupting delivery of the drive signals during the overload; an inverter apparatus characterized by monitoring a terminal voltage of said capacitor, and releasing the interlock operation on condition that the terminal voltage does not exceed a predetermined level.
Claim 3
Dependent Claim
39 words
An inverter apparatus according to claim 1, wherein the interlock operation is not released until a preset fixed time lapses after the detection of the overload of said inverter and the voltage said capacitor is below a predetermined value.