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US4727481A
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Memory addressing device
Assignee: Societe Anonyme de Telecommunications SAT
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Filing: 1984-11-13
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Granted: 1988-02-23
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Expires: 2004-11-13
Abstract
Abstract An addressing device for a memory, such as a dynamic memory ROM or RAM, addressable by address words at a predetermined clock-period rate. Each address word is made up of first and second address words composed of least significant and most significant bits of the address word respectively. The first and second address words are multiplexed. The device comprises an adding circuit for incrementing the first address words in terms of a predetermined digital signal carrying words that are synchronous with the first address words and for incrementing the second address word in each address word by unity whenever the first word of the address word has bits all equal to "1", and a shift circuit looped across the adding circuit in order to deliver the first and second multiplexed address words to the memory.
Inventors
- 👤 Gerard Aguille
- 👤 Jean-Claude R. Jolivet
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 11:56
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/04; G11C5/00; G11C5/06; G11C5/066
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
220 words
A device for sequentially addressing a memory with a stream of address words, the address words being successively delivered to the memory at a predetermined clock-period rate and each address word including first and second address words composed of least significant bits and most significant bits of the address word, respectively, the first and second address words being multiplexed, comprising (a) means for deriving a predetermined digital signal carrying words that are synchronous with the first address words; (b) means connected with said deriving means for receiving the first and second address words and said predetermined signal words for alternately incrementing the first and second address words into first and second incremented address words, respectively, the first address words being incremented in response to said predetermined signal words, respectively, and each of the second address words being incremented by 1 when the first address word included in the address word comprising the second address word has bits all equal to "1"; and (c) shift means looping said incrementing means for receiving first and second incremented address words and delivering them after a predetermined number of clock periods as new first and second address words to be incremented by said incrementing means, said first and second incremented address words successively produced by said incrementing means composing said stream of address words.
Claim 2
Independent Claim
220 words
A device for sequentially addressing a memory with a stream of address words, the address words being successively delivered to the memory at a predetermined clock-period rate and each address word including first and second address words composed of least significant bits and most significant bits of the address word, respectively, the first and second address words being multiplexed, comprising (a) means for deriving a predetermined digital signal carrying words that are synchronous with the first address words; (b) means connected with said deriving means for receiving the first and second address words and said predetermined signal words for alternately incrementing the first and second address words into first and second incremented address words, respectively, the first address words being incremented in response to said predetermined signal words, respectively, and each of the second address words being incremented by 1 when the first address word included in the address word comprising the second address word has bits all equal to "1"; and (c) shift means looping said incrementing means for receiving first and second incremented address words and delivering them after a predetermined number of clock periods as new first and second address words to be incremented by said incrementing means, said first and second incremented address words successively produced by said incrementing means composing said stream of address words.
Claim 3
Dependent Claim
120 words
Apparatus as defined in claim 1, wherein said incrementing means comprises (1) means for adding each first address word outgoing from said shift means and said predetermined digital signal word synchronous with the first address word into a first incremented address word entering said shift means; (2) means for detecting said first incremented address words carrying bits all equal to "1"; and (3) means for adding 1 to a second address word outgoing from said shift means into a second incremented address word inputting said shift means only when the first address word outgoing from said shift means and included in the address word comprising said second outgoing address word is being detected with all the bits equal to "1".
Claim 4
Dependent Claim
42 words
Apparatus as defined in claim 2, wherein the first and second address words each have P bits, where P is an integer, and wherein said adding means comprises a modulo-2 P adding circuit having a carry output connected to said detecting means.
Claim 5
Dependent Claim
69 words
Apparatus as defined in claim 3, wherein said detecting means comprises a flip-flop carrying an input delivering a "1" bit to a first input of said adding means through an OR gate whenever one of said first address words outgoing from said shift means and having bits all equal to "1" is fed to a second input of said adding means, said OR gate also receiving said predetermined signal.
Claim 6
Dependent Claim
93 words
Apparatus as defined in claim 1, wherein said predetermined digital signal carries binary coded words that are positive integers equal to or more than 0 and are synchronous with the first and second address words, respectively, a predetermined signal word equal to 0 being used for inhibiting any addition in said incrementing and repeating an address word means, equal to 1 being used for only adding 1 in said incrementing means so as to provide consecutive address words, and equal to an integer more than 1 being used for skipping consecutive address words.
Claim 7
Dependent Claim
31 words
Apparatus as defined in claim 1, wherein an address word is repeated by said incrementing means when a predetermined digital signal word equal to 0 is fed into said incrementing means.
Claim 8
Dependent Claim
35 words
Apparatus as defined in claim 1, wherein an address-word skip is made by said incrementing means when a predetermined digital signal word equal to an integer more than 1 is fed into the incrementing means.
Claim 9
Dependent Claim
39 words
Apparatus as defined in claim 1, wherein said shift means comprises at least two flip-flop stages that are timed on half of the clock period and are each capable of storing one of the first and second address words.
Claim 10
Dependent Claim
40 words
Apparatus as defined in claim 1, wherein said shift means comprises at least four flip-flop stages that are timed on a quarter of the clock period and are each capable of storing one of the first and second address words.
Claim 11
Dependent Claim
65 words
Apparatus as defined in claim 1, wherein said shift means comprises means receiving third address words and connected between outputs of said shift means and inputs of said incrementing means for replacing at least one of the address words by a third address word in order to synchronize at least one of the reading and writing operations in the memory from said third address word.
Claim 12
Dependent Claim
40 words
Apparatus as defined in claim 1, wherein during each clock period, one address word made up of a first and second word is only delivered by said device to said memory for simultaneously addressing the memory in reading and writing.
Claim 13
Dependent Claim
45 words
Apparatus as defined in claim 1, wherein during each clock period, one read address word and one write address word each composed of first and second address words are delivered by said device to the memory for alternating addressing the memory in reading and writing.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-02-22 | 1991-08-24 | 1992-02-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-02-22 | 1995-08-24 | 1996-02-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-02-22 | 1999-08-24 | 2000-02-23 | $7700.00 | Window Closed / Lapsed |