Sampled data filtering system, including a crossbar switch matrix, as for a ghost cancellation system

Claim 2

A sampled data signal filtering system, comprising: an input terminal for applying a sampled data input signal; sample delaying means, coupled to said input terminal and having N output terminals for providing, respectively, N sampled data signals representing said sampled data input signal delayed by N respectively different amounts of time, where N is an integer greater than 1; M sample scaling circuits, each having an input terminal coupled to receive one of said N sampled data signals, for multiplying said one sampled data signal by a scale factor, where M is an integer greater than 1 and less than N; crossbar switching means, coupled to said sample delaying means and to said M sample scaling circuits for coupling selected ones of the N output terminals of said sample delaying means to the input terminals of respectively different ones of said M sample scaling circuits; and means coupled to said M sample scaling circuits for summing the respective scaled sampled data signals provided thereby to generate a sampled data output signal.

Claim 3

The system set forth in claim 1 wherein, said crossbar switching means comprises: a matrix of switch elements having N rows and M columns wherein each row of switch elements in said matrix is coupled to a respectively different one of the N output terminals of said sample delaying means and each column of switch elements in said matrix is coupled to the input terminal of a respectively different one of said M sample scaling circuits; and control means, coupled to said matrix of switch elements for selectively enabling one switch element in each of said M columns of switch elements to thereby coupled selected output terminals of said sample delaying means to respectively different ones of said M sample scaling circuits.

Claim 4

A sampled data signal filtering system, comprising: an input terminal for applying a sampled data input signal; sample delaying means, coupled to said input terminal and having N output terminals for providing, respectively, N sampled data signals representing said sampled data input signal delayed by N respectively different amounts of time where N is an integer greater than 1; M sample scaling circuits, each having an input terminal coupled to receive one of said N sampled data signals, for multiplying M of said N sampled data signals by M respective scale factors, where M is an integer greater than 1 and less than N; a matrix of switch elements having N rows and M columns; first and second terminals for applying first and second control signals, respectively; means, responsive to said first control signal for providing a first enabling signal to the switch elements in a column of said matrix; and means, responsive to said second control signal for providing a second enabling signal to the switch elements in a column of said matrix; wherein each switch element in said matrix of switch elements includes: means, responsive to said first and second enabling signals for storing the value of said first enabling signal in a data storage element on the occurrence of said second enabling signal; and a transmission gate having a principal conduction path between a first electrode, coupled to one of the output terminals of said sample delaying means, and a second electrode, coupled to the input terminal of one of said sample scaling circuits, and having a third electrode which is responsive to the value stored in said data storage element for controlling the conductivity of said principal conduction path.

Claim 5

A sampled data signal filtering system, comprising: an input terminal for applying a sampled data input signal; sample delaying means, coupled to said input terminal and having N output terminals for providing, respectively, N sampled data signals representing said sampled data input signal delayed by N respectively different amounts of time where N is an integer greater than 1; M sample scaling circuits, each having an input terminal coupled to receive one of said N sampled data signals, for multiplying M of said N sampled data signals by M respective scale factors, where M is an integer greater than 1 and less than N; a matrix of switch elements having N rows and M columns; first and second terminals for applying first and second control signals, respectively; means, responsive to said first control signal for providing a first enabling signal to the switch elements in a column of said matrix; and means, responsive to said second control signal for providing a second enabling signal to the switch elements in a column of said matrix; wherein each switch element in said matrix of switch elements includes: means, responsive to said first and second enabling signals for storing the value of said first enabling signal in a data storage element on the occurrence of said second enabling signal; and a transmission gate having a principal conduction path between a first electrode, coupled to one of the output terminals of said sample delaying means, and a second electrode, coupled to the input terminal of one of said sample scaling circuits, and having a third electrode which is responsive to the value stored in said data storage element for controlling the conductivity of said principal conduction path.

Claim 6

The system set forth in claim 3 wherein said sample delaying means comprises N digital data storage elements, each having an input terminal and an output terminal and being configured as a shift register, wherein each of said N output terminals of said sample delaying means corresponds to a respectively different one of the output terminals of said N digital data storage elements.

Claim 7

In a sampled data filtering system, including N serially connected delay elements and M sample scaling circuits where N and M are integers greater than one and M is less than N, circuitry for coupling selected ones of said delay elements to said sample scaling circuits to generate scaled sampled data output signals, comprising: a matrix of switch elements having N rows and M columns, wherein each row of switch elements in said matrix is coupled to a respectively different one of said delay elements and each column of switch elements in said matrix is coupled to a respectively different one of said sample scaling circuits; and control means, coupled to said matrix of switch elements for selectively enabling one switch element in each column of switch elements to thereby couple the delay elements coupled to the respective selected switch elements to the sample scaling circuits coupled to the respective selected switch elements.

Claim 8

In a sampled data filtering system, including N serially connected delay elements and M sample scaling circuits where N and M are integers greater than one and M is less than N, circuitry for coupling selected ones of said delay elements to said sample scaling circuits to generate scaled sampled data output signals, comprising: a matrix of switch elements having N rows and M columns, wherein each row of switch elements in said matrix is coupled to a respectively different one of said delay elements and each column of switch elements in said matrix is coupled to a respectively different one of said sample scaling circuits; and control means, coupled to said matrix of switch elements for selectively enabling one switch element in each column of switch elements to thereby couple the delay elements coupled to the respective selected switch elements to the sample scaling circuits coupled to the respective selected switch elements.

Claim 9

The circuitry set forth in claim 5 wherein: said control means includes: first and second terminals for applying first and second control signals; means, responsive to said first control signal, for providing a first enabling signal to the switch elements in a row of said matrix; and means, responsive to said second control signal, for providing a second enabling signal to the switch elements in a column of said matrix; and each switch element in said matrix of switch elements includes: means, responsive to said first and second enabling signals for storing the value of said first enabling signal in a data storage element on the occurrence of said second enabling signal; and a transmission gate having a principal conduction path between a first electrode, coupled to the output terminal of one of said delay elements, and a second electrode, coupled to the input terminal of one of said sample scaling circuits, and having a third electrode which is responsive to the value stored in said data storage element for controlling the conductivity of said principal conduction path.