Patent US4727335A successfully refreshed from Google Patents.
US4727335A
Expired / Lapsed
US
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Gain-controlled amplifier
Assignee: Nippon Gakki Co Ltd
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Filing: 1986-09-17
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Granted: 1988-02-23
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Expires: 2006-09-17
Abstract
Abstract A gain-controlled amplifier amplifies an input signal at a gain which varies exponentially in accordance with a control voltage applied thereto and selectively outputs one of non-inverted and inverted output signals substantially identical in characteristic with each other. The gain-controlled amplifier comprises first and second transistor pairs, a common emittor driving circuit and a subtracting circuit. The first transistor pair comprises first and second transistors, and the second transistor pair comprises third and fourth transistors. The emittors of each of the transistor pairs are joined together, and bases of the first and third transistors and bases of second and fourth transistors are joined together, respectively. The two sets of joined bases serve as input terminals of the control voltage. The common emitter driving circuit complementalily drives each of the joined emitters in accordance with the input signal of the amplifier. Connected to the collectors of the first and third transistors and the collectors of the second and fourth transistors are a current-mirror circuit and resistors, respectively, as loads. A current is supplied to the collector of the first transistor in accordance with the input signal. The subtracting circuit subtracts a signal appearing at a collector of one of the second and fourth transistors from a signal appearing at a collector of the other of the second and fourth transistors, and outputs the subtraction result as the output signal of this amplifier.
Inventors
- 👤 Kenji Yokoyama
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 18:50
CPC Classifications
H; H03; H03G; H03G3/00; H03G3/02; H03G3/04; H03G3/10; H03G1/00; H03G1/0005; H03G1/0017; H03G1/0023
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
238 words
A gain-controlled amplifier for amplifying an input signal at a gain which is controlled by a control voltage applied thereto comprising: an input terminal for receiving an input signal; an output terminal for providing an output signal; a first bipolar transistor pair having first and second transistors, the emitters of which are connected to each other, the control voltage being applied between bases of said first and second transistors; means for supplying a current to a collector of said first transistor, said current corresponding to the input signal; a second bipolar transistor pair having third and fourth transistors, the emitters of which are connected to each other, the control voltage being applied between bases of said third and fourth transistors; a current-mirror circuit connected to said collector of said first transistor and a collector of said third transistor as loads; first and second resistors having the same resistance and connected to collectors of said second and fourth transistors as loads, respectively; a common emitter driving circuit for complementarily driving both common emitters of said first and second bipolar transistor pairs in accordance with the input signal; and subtracting circuit means for subtracting a signal appearing at said collector of one of said second and fourth transistors from a signal appearing at said collector of the other of said second and fourth transistors, said subtracting circuit means providing a subtraction result to the output terminal as the output signal.
Claim 2
Dependent Claim
238 words
A gain-controlled amplifier for amplifying an input signal at a gain which is controlled by a control voltage applied thereto comprising: an input terminal for receiving an input signal; an output terminal for providing an output signal; a first bipolar transistor pair having first and second transistors, the emitters of which are connected to each other, the control voltage being applied between bases of said first and second transistors; means for supplying a current to a collector of said first transistor, said current corresponding to the input signal; a second bipolar transistor pair having third and fourth transistors, the emitters of which are connected to each other, the control voltage being applied between bases of said third and fourth transistors; a current-mirror circuit connected to said collector of said first transistor and a collector of said third transistor as loads; first and second resistors having the same resistance and connected to collectors of said second and fourth transistors as loads, respectively; a common emitter driving circuit for complementarily driving both common emitters of said first and second bipolar transistor pairs in accordance with the input signal; and subtracting circuit means for subtracting a signal appearing at said collector of one of said second and fourth transistors from a signal appearing at said collector of the other of said second and fourth transistors, said subtracting circuit means providing a subtraction result to the output terminal as the output signal.
Claim 3
Dependent Claim
36 words
A gain-controlled amplifier according to claim 1, wherein said means for supplying a current to said collector of said first transistor comprises a resistor connected between the input terminal and said collector of said first transistor.
Claim 4
Dependent Claim
88 words
A gain-controlled amplifier according to claim 1, wherein said current-mirror circuit comprises fifth and sixth bipolar transistors whose bases are connected to each other and connected to the collector of one of said fifth and sixth transistors, a third resistor connected between an emitter of said fifth transistor and a first power supply and a fourth resistor connected between an emitter of said sixth transistor and said first power supply, collectors of said fifth and sixth transistors being connected to said collectors of said first and third transistors.
Claim 5
Dependent Claim
64 words
A gain-controlled amplifier according to claim 1, wherein said common emitter driving circuit comprises first and second additional bipolar transistors whose emitters are connected together, collectors of said first and second additional transistors being connected respectively to said common emitters of said first and second transistor pairs, bases of said first and second additional transistors being complementarily driven in accordance with the input signal.
Claim 6
Dependent Claim
74 words
A gain-controlled amplifier according to claim 4, wherein said common emitter driving circuit further comprises a first differential amplifier having third and fourth additional bipolar transistors, the emitters of which are connected to each other, said emitters of said third and fourth additional transistors being supplied with a current from a constant current circuit, collectors of said third and fourth additional transistors being connected to said bases of said first and second additional transistors.
Claim 7
Dependent Claim
90 words
A gain-controlled amplifier according to claim 1, further comprising buffer amplifier means for feeding said signals appearing at said collectors of said second and fourth transistors to said subtracting circuit means, said buffer amplifier means comprising first and second supplementary transistors and two constant current sources for causing constant currents to flow through emitters of said first and second supplementary transistors connected to said collectors of said second and fourth transistors, signals appearing at said emitters of said first and second supplementary transistors being supplied to said subtracting circuit means.
Claim 8
Dependent Claim
233 words
A gain-controlled amplifier according to claim 1, further comprising a first buffer for amplifying said signal appearing at the collector of said second transistor to output an amplified signal from a first terminal and a second buffer for amplifying said signal appearing at the collector of said fourth transistor to output an amplified signal from a second terminal, and wherein said subtracting circuit means comprises a third terminal for being selectively connected to one of said first and second terminals, a fourth terminal for being selectively connected to the other of said first and second terminals, third and fourth additional resistors having the same resistance and serially connected between said third terminal and said output terminal, fifth and sixth additional resistors identical in resistance value to said third and fourth additional resistors and serially connected between said fourth terminal and ground, and an operational amplifier having inverting and non-inverting inputs, the inverting input terminal being connected to a junction point of said third and fourth additional resistors, the non-inverting input terminal of said operational amplifier being connected to a junction point of said fifth and sixth additional resistors, an output terminal of said operational amplifier being connected to said output terminal whereby the characteristics of the output signal will be either in phase or 180° out of phase depending on the selected connections with signal characteristics which are otherwise identical for either connection.
References Cited (Backward Citations)
US4331929A
Cited
JPS5646313A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-02-22 | 1991-08-24 | 1992-02-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-02-22 | 1995-08-24 | 1996-02-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-02-22 | 1999-08-24 | 2000-02-23 | $7700.00 | Window Closed / Lapsed |