Transient detector apparatus

Claim 1

A transient detector appartus comprising in combination: an input monitor probe to receive an input signal, said input signal comprising a logic signal and a transient signal, a signal conditioner means to receive said input signal from said input monitor probe, said signal conditioner means determining the correct logic level of the digital bits in said input signal, said signal conditioner means generating a corrected logic input signal, means for detecting slope receiving said corrected logic input signal from said signal conditioner means, said slope detecting means determining the slope of said corrected logic input signal, said slope detecting means providing a digital pulse signal proprtional to the slope of said corrected logic input signal, a means for switching connected to said signal conditioner means to receive said corrected logic input signal therefrom, first and second peak detector means respectively connected to said switching means for receiving said corrected logic input signal therefrom, said switching means alternating the application of said corrected logic input signal to said first and second peak detector means depending upon the state of said first and second peak detector means, said first and second peak detector means detecting and storing the peak value of the corrected logic input signal applied thereto, a means for generating logic signals connected to said slope detecting means for receiving said digital pulse signal therefrom, said logic means determining whether said digital pulse signal represents a logic or a transient pulse, said logic means generating a validate signal when a transient pulse is determined, said logic means generating a restore signal when a logic pulse is determined, a control means receiving said validate or restore signal from said logic means, said control means monitoring said peak value in said first and second peak detector means, said control means signals either said first or second peak detector means to output said peak value when a validate signal has been received by one peak detector means and a larger value transient signal is received by the other peak detector means, an A/D converter means connected respectively to said first and second peak detector means to receive the peak value therefrom, said A/D converter means generating a digital amplitude signal in proportion to said peak value, a timing means receiving external synch signals, said timing means providing timing signals respectively to said logic means, said switching means, and said A/D converter means, a counter means connected to said slope detecting means to receive said digital pulse signal therefrom, said counter means receiving a control signal from said logic means, a width register means connected to said counter means, said counter means applying said digital pulse signal to said width register means upon receipt of said control signal from said logic means, and, an amplitude register means connected to said A/D converter means to receive said digital amplitude signal therefrom, said amplitude register means providing an amplitude output signal.